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muslic multichannel subscriber line interface concept peb 3465 version 1.2 peb 31666/31664 version 1.3 peb 4166/4164 version 2.3 never stop thinking. wired communications preliminary data sheet, ds1, july 2000
edition 2000.07.06 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 18. 8. 00. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
p r e l i m in a r y wired communications muslic multichannel subscriber line interface concept peb 3465 version 1.2 peb 31666/31664 version 1.3 peb 4166/4164 version 2.3 preliminary data sheet, ds1, july 2000 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com/products muslic preliminary revision history: 2000.07.06 ds1 previous version: preliminary data sheet ds1 page subjects (major changes since last revision) page 50 version register added to table 6 . page 51 status register: bit sample_rdy added. page 52 figure 22 ?reading of sample results? added. page 49 interrupt (intr) signal active level for intel mode and motorola mode added. page 54 table 7 ?interrupt register?: ?idle? added. further description added. page 56 former chapter 3.2.3 ?interrupt timing? including former figure ?interrupt timing? removed. page 57 figure 25 ?interrupt handling (first step)? added. page 58 figure 26 ?interrupt handling (second step - interrups in one channel)? added. page 59 figure 27 ?interrupt handling (second step - interrupts in two or more channels)? added. page 75 configuration register scr3: bits modem, usgain and zswitch added. page 84 bits mo, m1, m2: note on pin io1 of the qap added. page 104 extended operation test register xtr6: bit gainbb added, description for bit ditoff changed, table 10 "important factors by using muslicos" added. page 122 table 11 operating modes muslic-e added page 131 unbalanced ringing: description on improved support of external ringing delay added.
peb 3465, peb 31666/4, peb 4166/4 muslic table of contents page preliminary data sheet 5 2000.07.06 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 peb 3465 (qap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.1 logic symbol (peb 3465) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.2 pin configuration (peb 3465) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2.3 pin definition and functions (peb 3465) . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.4 functional block diagram (peb 3465) . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3 peb 31666/4 (mupp c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.1 logic symbol (peb 31666/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.2 pin configuration (peb 31666/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.3 pin definitions and functions (peb 31666/4) . . . . . . . . . . . . . . . . . . . . 22 1.3.4 functional block diagram (peb 31666/4) . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 peb 4166/4 (ahv-slic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.1 logic symbol (peb 4166/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.2 pin configuration (peb 4166/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.3 pin definition and functions (peb 4166/4) . . . . . . . . . . . . . . . . . . . . . . 28 1.4.4 functional block diagram (peb 4166/4) . . . . . . . . . . . . . . . . . . . . . . . . 30 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.1 principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.1.1 signal flow graph: ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.1.2 signal flow graph: dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.1.3 ahv-slic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.1.3.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.1.3.2 current limitation / overtemperature . . . . . . . . . . . . . . . . . . . . . . . . 42 3 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1 pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.1 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.2 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.3 mupp c/qap interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.4 qap/ahv-slic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4 programming the muslic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.1 types of c interface bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1.1 sop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.1.2 xop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.1.3 top command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.1.4 cop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.1.5 copi command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.1 reset behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
peb 3465, peb 31666/4, peb 4166/4 muslic table of contents page preliminary data sheet 6 2000.07.06 5.2 basic setting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.3 power down (pdown) and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.4 active mode (act) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.5 ringing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.6 ground start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.7 changing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6 transmission characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.1 transmission values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.2 frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 6.3 gain tracking (receive and transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.4 group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.5 overload compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.6 total distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.7 out-of-band signals at analog output (receive) . . . . . . . . . . . . . . . . . . 146 6.8 out-of-band signals at analog input (transmit) . . . . . . . . . . . . . . . . . . . 147 6.9 out-of-band ringing distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.10 terminal balance return loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7 test features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.1 peb 3465 (qap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.2 peb 31666 / peb 31664 (mupp c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 8.3 peb 4166 / peb 4164 (ahv-slic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
peb 3465, peb 31666/4, peb 4166/4 muslic list of figures page preliminary data sheet 7 2000.07.06 figure 1 logic symbol (peb 3465) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2 pin configuration (peb 3465) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3 functional block diagram (peb 3465) . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4 logic symbol (peb 31666/4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5 pin configuration (peb 31666/4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6 functional block diagram (peb 31666/4) . . . . . . . . . . . . . . . . . . . . . . 25 figure 7 logic symbol (peb 4166/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8 pin configuration (peb 4166/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9 functional block diagram (peb 4166/4) . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10 central office analog linecard for 16 subscribers . . . . . . . . . . . . . . . 31 figure 11 typical application circuit of the muslic chip set . . . . . . . . . . . . . . . 32 figure 12 signal flow graph: ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13 signal flow graph: dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 14 dc characteristic in normal battery mode . . . . . . . . . . . . . . . . . . . . . 38 figure 15 definition of output current directions . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16 example for single clock rate, 512 kb/s. . . . . . . . . . . . . . . . . . . . . . . 44 figure 17 example for double clock rate, 512 kb/s . . . . . . . . . . . . . . . . . . . . . . 45 figure 18 2048 kb/s, single clock operation, only highway a used . . . . . . . . . . 46 figure 19 detail a in figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 20 pcm-group delay transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 21 pcm-group delay receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 22 reading of sample results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 23 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 24 mupp c/qap interface: frame, bit structure . . . . . . . . . . . . . . . . . . 56 figure 25 interrupt handling (first step) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 26 interrupt handling (second step - interrupts in one channel) . . . . . . . 58 figure 27 interrupt handling (second step - interrupts in two or more channels) 59 figure 28 checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 29 interrupt logic (block structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 30 overview of coefficient sets (fix-chan = 0 in xr2) . . . . . . . . . . . . 116 figure 31 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 32 transmission characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 33 voltage amplitude of teletax metering . . . . . . . . . . . . . . . . . . . . . . . 139 figure 34 frequency response transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 35 frequency response receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 36 gain tracking (receive and transmit) . . . . . . . . . . . . . . . . . . . . . . . 141 figure 37 group delay distortion (receive and transmit) . . . . . . . . . . . . . . . . 142 figure 38 overload compression transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 39 total distortion receive ar = 7 dbr . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 40 total distortion transmit ax = 0 dbr . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 41 out-of-band signals at analog output (receive) . . . . . . . . . . . . . . . 146 figure 42 out-of-band signals at analog input (transmit) . . . . . . . . . . . . . . . . 147
peb 3465, peb 31666/4, peb 4166/4 muslic list of figures page preliminary data sheet 8 2000.07.06 figure 43 out-of-band ringing distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 44 package outline: peb 3465 (qap) . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 45 package outline: peb 31666 / peb 31664 (mupp c) . . . . . . . . . . 152 figure 46 package outline: peb 4166 / peb 4164 (ahv-slic) . . . . . . . . . . . . 153
peb 3465, peb 31666/4, peb 4166/4 muslic list of tables page preliminary data sheet 9 2000.07.06 table 1 muslic chip set ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2 list of components in typical application circuit ( figure 11 ). . . . . . . 33 table 3 programming of operating modes (pin c3 = 0 v or open) . . . . . . . . . 41 table 4 programming of operating modes (pin c3 = 5 v) . . . . . . . . . . . . . . . . 41 table 5 pcm interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 6 possible address information to identify the following data nibbles . 50 table 7 interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 8 storage of programming information . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 9 analog gain combinations with qap v1.2 or higher. . . . . . . . . . . . . . 76 table 10 important factors for the calculation of voltages and slopes in different modes by using muslicos 105 table 11 operating modes muslic-e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 12 default dc values (fixc ( xr2 bit 4) = 1). . . . . . . . . . . . . . . . . . . . . 125 table 13 default ac values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 14 group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 15 levelmeter-function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 10 2000.07.06 preliminary 1introduction the muslic, a chip set of three highly sophisticated ics, bridges the gap between the analog and the digital signal transmission in modern telecommunication systems. this highly integrated chip set supports to realize an extremely compact analog subscriber line interface module. only a few external components are required and there is no trimming or adjustment necessary to meet worldwide recommendations. each device is made of the best fitting technology (cmos, bicmos and smart power technology) and the standard smd-packages p-mqfp and p-dso are used. the chip set consists of three out of seven available ics: note: the term "mupp-c" in this document applies to both chips mupp c-e (peb 31666) and mupp c-s (peb 31664). the term ahv-slic applies to both chips ahv-slic-e (peb 4166) and ahv-slic-s (peb 4164). this document describes the combination of mupp c, qap and ahv-slic in detail. the combination of mupp iom-2, qap and ahv-slic (peb 4165) is described within a second document. nevertheless, other possible combinations of mupp and ahv- slic devices can also be implemented. note: for more detailed description please refer to the muslic chip set selection guide and the application note "differences between muslic-e and muslic-s". table 1 muslic chip set ics peb 31664 peb 31665 peb 31666 mupp c-s mupp iom ? -2 mupp c-e multichannel processor for pots peb 3465 qap quad analog pots peb 4164 peb 4165 peb 4166 ahv-slic-s ahv-slic ahv-slic-e advanced high voltage subscriber line circuit
p-mqfp-80-1 multichannel subscriber line interface concept muslic peb 3465 peb 4166/4 peb 31666/4 preliminary data sheet 11 2000.07.06 bicmos, cmos, smart power type package peb 3465 v1.2 p-mqfp-80-1 peb 31666/4 v1.3 p-mqfp-64-1 peb 4166/4 v2.3 p-dso-20-5 preliminary p-mqfp-64-1 p-dso-20-5 1.1 features chip set of three well fitted chips optimized for a 16 pots-base system including all low and high voltage slic functions only a few external components are required no trimming or adjustments are required specification according to relevant itu-t q.552 z interface, lssgr and dtag recommendations digital signal processing technique advanced low power cmos and bicmos 1) and smart power technology pcm encoded digital voice transmission (a-law , ?law and linear) 8 bits parallel microcontroller interface for intel- and motorola-like processors multiplexed and demultiplexed address/data bus mode possible high performance ad and da conversion programmable digital filters for ? impedance matching ? transhybrid balancing ? frequency response ? gain advanced test capabilities (peb31666 only) ? integrated line and circuit tests ? two programmable tone generators 1) abbreviations see chapter 9
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 12 2000.07.06 preliminary fully digital programmable dc-characteristic ? programmable constant current from 0 to 70 ma for muslic s2/e2 ? programmable resistive values from 0 to 2 800 ? ? programmable constant voltage programmable integrated teletax injection and filtering during active in on-hook and off-hook (peb 31666 only): ? programmable up to 10 vrms at ring/tip-wire of the ahv-slic ? programmable frequency (12/16 khz) polarity reversal (programmable soft or hard) integrated (balanced) ringing generation with zero crossing injection (peb 4166 only): ? programmable frequency between 16.6 and 70 hz ? programmable amplitude up to 85 vrms at ring/tip-wire of the ahv-slic three operating modes: power down, active and ringing off-hook detection with programmable thresholds for all operating modes integrated ring trip detection with zero crossing turn off function ground start and loop start possible integrated checksum calculation for cram (ac and dc separated) linecard identification sensing of transversal and longitudinal line current battery voltage ? 15 v ? ? 80 v; auxiliary voltage + 5 v ? + 85 v (peb 4166 only). second negative battery voltage for power saving at short lines boosted battery mode with up to 150 v supply for long telephone lines and up to 85 vrms balanced ringing (peb 4166 only) reliable 170 v smart power technology standard smd packages: p-mqfp-64-1 and p-mqfp-80-1 for the low voltage parts and small power package p-dso-20-5 for the high voltage device
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 13 2000.07.06 preliminary 1.2 peb 3465 (qap) 1.2.1 logic symbol (peb 3465) figure 1 logic symbol (peb 3465) it-a adu add afsc reset peb 3465 16,384 mhz interface qap reset 72 73 74 54 53 52 47 71 adcl 51 adr 48 itac-a vr-a il-a dcp-a dcn-a acp-a acn-a 76 77 78 75 transmit channel a receive channel a 79 80 c2-a c1-a supervision channel a transmit channel c receive channel c supervision channel c transmit channel b receive channel b supervision channel b transmit channel d receive channel d supervision channel d i/o1-a 4 i/o2-a 5 i1-a 6 o1-a 2 i/o-pins channel a i/o-pins channel b i/o-pins channel c i/o-pins channel d va 10 vb 9 rref 14 vbim 8 1 3 vdd-a gnd-a transmit channel a supply channel a supply channel b supply channel c supply channel d digital supply vddi gndi 49 50 analog inputs select qap vddz gndz 12 11 vss 13 central analog supply ezm07000.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 14 2000.07.06 preliminary 1.2.2 pin configuration (peb 3465) figure 2 pin configuration (peb 3465) 1 2 3 4 5 6 7 8 9 1011121314151617181920 21 22 23 24 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 66 65 80 79 78 77 76 75 74 73 72 71 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 61 62 63 64 c1-a c2-a vdd-a o1-a gnd-a i/o1-a i/o2-a i1-a nc vbim vb va vddz gndz vss rref i1-b i/o2-b i/o1-b gnd-b o1-b vdd-b c2-b c1-b c1-d c2-d vdd-d o1-d gnd-d i/o1-d i/o2-d i1-d adu add afsc adcl vddi gndi adr reset i1-c i/o2-c i/o1-c gnd-c o1-c vdd-c c2-c c1-c acn-b acp-b dcn-b dcp-b il-b vr-b itac-b it-b it-c itac-c vr-c il-c dcp-c dcn-c acp-c acn-c acn-a acp-a dcn-a dcp-a il-a vr-a itac- a it-a it-d itac-d vr-d il-d dcp-d dcn-d acp-d acn-d peb 3465 p-mqfp-80-1 ezm07001.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 15 2000.07.06 preliminary 1.2.3 pin definition and functions (peb 3465) the following tables group the pins according to their functions. they include pin number, pin name, type and a brief description of the function. pin no. name type function power supply pins 1vdd-a ? + 5 v analog supply voltage (channel a) 20 vdd-b ? + 5 v analog supply voltage (channel b) 41 vdd-c ? + 5 v analog supply voltage (channel c) 60 vdd-d ? + 5 v analog supply voltage (channel d) 3 gnd-a ? analog ground (channel a) 18 gnd-b ? analog ground (channel b) 43 gnd-c ? analog ground (channel c) 58 gnd-d ? analog ground (channel d) 11 vddz ? + 5 v analog supply voltage (bias) 12 gndz ? analog ground (bias) 13 vss ?? 5 v analog supply voltage 50 vddi ? digital supply voltage (+ 3.3 v or +5 v) 49 gndi ? digital ground interface pins to mupp c (peb 31666/4) 54 adu o analog data upstream 53 add i analog data downstream 51 adcl i analog data-clock 52 afsc i analog frame sync. 48 adr i select odd or even port nr. 47 reset i interface-reset (active high)
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 16 2000.07.06 preliminary interface to ahv-slic (peb 4166/4) 71 it-a i transversal current input (ac+dc), channel a 72 itac-a i transversal current input (ac), channel a 73 vr-a i reference input, channel a 74 il-a i longitudinal current input, channel a 77 acp-a o two wire output voltage (acp), channel a 78 acn-a o two wire output voltage (acn), channel a 75 dcp-a o two wire output voltage (dcp), channel a 76 dcn-a o two wire output voltage (dcn), channel a 79 c1-a i/o digital interface to ahv-slic, channel a 80 c2-a o digital interface to ahv-slic, channel a 30 it-b i transversal current input (ac+dc), channel b 29 itac-b i transversal current input (ac), channel b 28 vr-b i reference input, channel b 27 il-b i longitudinal current input, channel b 24 acp-b o two wire output voltage (acp), channel b 23 acn-b o two wire output voltage (acn), channel b 26 dcp-b o two wire output voltage (dcp), channel b 25 dcn-b o two wire output voltage (dcn), channel b 22 c1-b i/o digital interface to ahv-slic, channel b 21 c2-b o digital interface to ahv-slic, channel b 31 it-c i transversal current input (ac+dc), channel c 32 itac-c i transversal current input (ac), channel c 33 vr-c i reference input, channel c 34 il-c i longitudinal current input, channel c 37 acp-c o two wire output voltage (acp), channel c 38 acn-c o two wire output voltage (acn), channel c 35 dcp-c o two wire output voltage (dcp), channel c 36 dcn-c o two wire output voltage (dcn), channel c 39 c1-c i/o digital interface to ahv-slic, channel c pin no. name type function
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 17 2000.07.06 preliminary 40 c2-c o digital interface to ahv-slic, channel c 70 it-d i transversal current input (ac+dc), channel d 69 itac-d i transversal current input (ac), channel d 68 vr-d i reference input, channel d 67 il-d i longitudinal current input, channel d 64 acp-d o two wire output voltage (acp), channel d 63 acn-d o two wire output voltage (acn), channel d 66 dcp-d o two wire output voltage (dcp), channel d 65 dcn-d o two wire output voltage (dcn), channel d 62 c1-d i/o digital interface to ahv-slic, channel d 61 c2-d o digital interface to ahv-slic, channel d io pins 1) 4 io1-a i/o user-programmable i/o pin, channel a 5io2-a 2) i/o user-programmable i/o pin, channel a 6 i1-a i fixed input pin, channel a 2 o1-a o fixed output pin, channel a 17 io1-b i/o user-programmable i/o pin, channel b 16 io2-b 2) i/o user-programmable i/o pin, channel b 15 i1-b i fixed input pin, channel b 19 o1-b o fixed output pin, channel b 44 io1-c i/o user-programmable i/o pin, channel c 45 io2-c 2) i/o user-programmable i/o pin, channel c 46 i1-c i fixed input pin, channel c 42 o1-c o fixed output pin, channel c 57 io1-d i/o user-programmable i/o pin, channel d 56 io2-d 2) i/o user-programmable i/o pin, channel d 55 i1-d i fixed input pin, channel d 59 o1-d o fixed output pin, channel d pin no. name type function
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 18 2000.07.06 preliminary miscellaneous function pins 14 rref o test pin, do not connect 10 va i voltage sense a 9 vb i voltage sense b 8 vbim i battery image sense input pins not used 7n.c. ? not connected (not used) 1) unused fixed input pn shave to terminated with pull up or pull down. unused programmable pins chould be programmed to output. 2) if the peb3465 is used together with the ahv-slics peb4164 or peb4166 it is recommended to use the io2- pin to drive the c3-pin of the ahv-slic. pin no. name type function
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 19 2000.07.06 preliminary 1.2.4 functional block diagram (peb 3465) figure 3 functional block diagram (peb 3465) channel a channel b channel c channel d common bias itac acp acn c1 c2 dcp it prefi s d a / d d / a buffer hw - filter hw - filter im prefi s d a / d hw - filter buffer d / a hw - filter dc - path ( 1 channel ) ac - path ( 1 channel ) hv- interface a / d supervision & i/o ( 1 channel ) vdd gnd itac acp acn c1 c2 dcp it vdd gnd rref interface for 4 channels dcn il vddi gndi vr vr dcn il itac acp acn c1 c2 dcp it vdd gnd vr dcn il itac acp acn c1 c2 dcp it vdd gnd vr dcn il vss gndz vddz va vb vbim add adu afsc adcl adr reset i / o i/o1 i1 o1 i/o2 channel a ezm07002.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 20 2000.07.06 preliminary 1.3 peb 31666/4 (mupp c) 1.3.1 logic symbol (peb 31666/4) figure 4 logic symbol (peb 31666/4) ezm07101.emf peb 31666 peb 31664 microcontroller interface qap interface mupp c fsc pclk dra dxa drb dxb io1 io2 tst1 id3 id2 id1 id0 io4 io3 pcm interface testpin user-programmable i/o pins external identifikation tca tcb mclk gndp gnd vdd vddp vdd5 power supply efsc reset adu1 add1 afsc adcl add2 adu2 csq wrq dio0 dio1 dio2 dio3 ale / dsq rdq / rwq a6 a7 a3 a4 a5 a0 a1 a2 muxq intq / mot dio5 dio6 dio7 dio4 intr
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 21 2000.07.06 preliminary 1.3.2 pin configuration (peb 31666/4) figure 5 pin configuration (peb 31666/4) 1 2 345678910 11 peb 31666 peb 31664 p-mqfp-64-1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 io4 mclk tca dra dxa pclk vdd gnd tcb drb dxb reset io3 fsc add1 adu1 afsc adcl gndp vddp vdd gnd io2 id0 id1 id2 id3 efsc adu2 add2 io1 tst1 wrq rdq/rwq ale/dsq csq gnd vdd dio0 dio1 dio2 dio3 gnd vdd dio4 dio5 dio6 dio7 vdd5 intr muxq/demux intq/mot gnd vdd a0 a1 a2 a3 a4 a5 a6 a7 vdd gnd ezm07102.emf
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 22 2000.07.06 preliminary 1.3.3 pin definitions and functions (peb 31666/4) the following tables group the pins according to their functions. they include pin number, pin name, type and a brief description of the function. pin no. name type function power supply pins 8, 22, 33, 44, 54, 60 gnd ? digital ground 19 gndp ? digital ground for pll 7, 21, 34, 43, 53, 59 vdd ? + 3.3 v digital supply voltage 20 vddp ? + 3.3 v digital supply voltage for pll 48 vdd5 ? + 5 v digital supply voltage pcm pins 3 tca o transmit control output for highway a, open drain 4 dra i receive data for highway a 5 dxa o transmit data for highway a 9 tcb o transmit control output for highway b, open drain 10 drb i receive data for highway b 1) 11 dxb o transmit data for highway b 6pclkipcm-clock 1) if unused, terminate input pins with pull-up or pull-down
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 23 2000.07.06 preliminary mupp c/qap interface 15 add1 o 1st qap-bus data downstream 16 adu1 i 1st qap-bus data upstream 1) 17 afsc o qap frame sync 18 adcl o qap data-clock 30 add2 o 2nd qap-bus data downstream 29 adu2 i 2nd qap-bus data upstream 1) 1) in case only 8 channels are used, terminate adux with an pull up of approx. 10kohm. microcontroller interface 2 mclk i master-clock (4.096 mhz) 14 fsc i frame sync 42 a0 i address 0 41 a1 i address 1 40 a2 i address 2 39 a3 i address 3 38 a4 i address 4 37 a5 i address 5 36 a6 i address 6 35 a7 i address 7 61 csq i ? chip select (active low) 62 ale /dsq i c address latch enable / dataselect (active low), (motorola) 63 rdq / rwq i c data-clock read (active low)/ read-write (motorola) 64 wrq i c data-clock write (active low) 46 muxq / demux i c multiplex / demultiplex mode 45 intq / mot i ? intel / motorola mode 58 dio0 i/o c data / address 57 dio1 i/o c data / address pin no. name type function
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 24 2000.07.06 preliminary 56 dio2 i/o c data / address 55 dio3 i/o c data / address 52 dio4 i/o c data / address 51 dio5 i/o c data / address 50 dio6 i/o c data / address 49 dio7 i/o c data / address 47 intr o interrupt io pins 31 io1 i/o user-programmable i/o pin 23 io2 i/o user-programmable i/o pin 13 io3 i/o user-programmable i/o pin 1 io4 i/o user-programmable i/o pin miscellaneous function pins 12 reset i reset (active high) 24 id0 i external identification. serial data input for external device (see ? xr7 and xr8 extended operation register 7 to 8 ? on page 96 ) 25 id1 i must be set to 1 for external identification 26 id2 i must be set to 1 for external identification 27 id3 i must be set to 1 for external identification 28 efsc o external asic frame sync 32 tst1 i test pin (for normal operation it must be connected to gnd) 2 mclk i master clock 4.096 mhz 14 fsc i frame sync pin no. name type function
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 25 2000.07.06 preliminary 1.3.4 functional block diagram (peb 31666/4) figure 6 functional block diagram (peb 31666/4) fsc wrq ale dio0..7 rdq csq ecic id0..3 i/o qap inter- face power up reset pll clk gen io1..4 test tst1 adu1 add1 afsc adcl adu2 add2 reg dp ram 1 dc- contr. dsp dp ram 2 flags dc- dsp cram ttx dsp cram b 2b ac- dsp (64k-32k) cram ac- dsp (32k-8k) cram comp. exp. dc cntl ac reset voice coeff. flags dc- feeding control monitor, c/i monitor (coeff.) monitor ( coeff .) voice lm c tca dra dxa control c/i mon. intr tcb drb pclk dxb pcm voice a0..7 muxq/demux intq/mot mclk ezm07119.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 26 2000.07.06 preliminary 1.4 peb 4166/4 (ahv-slic) 1.4.1 logic symbol (peb 4166/4) figure 7 logic symbol (peb 4166/4) tip ring vh *) vbat vbat2 bgnd vdd agnd vss supfi it il acp acn dcp dcn c1 c2 peb 4166 peb 4164 ahv-slic c3 *) for the peb 4164 this pin must not be connected. ezm07103.emf
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 27 2000.07.06 preliminary 1.4.2 pin configuration (peb 4166/4) figure 8 pin configuration (peb 4166/4) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 vbat ring tip bgnd vh *) vdd c1 c2 supfi vbat c3 il it vss agnd acn acp dcn dcp vbat2 peb 4166 peb 4164 p-dso20-5 *) for the peb 4164 this pin must not be connected. ezm07104.emf
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 28 2000.07.06 preliminary 1.4.3 pin definition and functions (peb 4166/4) the following tables group the pins according to their functions. they include pin number, pin name, type and a brief description of the function. pin no. symbol type description power supply pins 1,10 vbat ? negative battery supply voltage ( ? 15 ?? 80 v), referred to bgnd 11 vbat2 ? second negative battery supply voltage ( ? 15 v vbat2 vbat); allows power saving at short lines. if unused connect to vbat. 5vh *) ? auxiliary positive battery supply voltage (+ 5 ? +85v) used in ringing mode. if unused connect to vdd. 4bgnd ? battery ground: tip, ring, vbat, vbat2 and vh refer to this pin 6vdd ? positive supply voltage (+ 5 v), referred to agnd 17 vss ? negative supply voltage ( ? 5 v), referred to agnd 16 agnd ? analog ground: vdd, vss and all signal and control pins with the exception of tip and ring refer to agnd *) for the peb 4164 the pin vh is internal connected to vdd; so it must not be connected externally. line interface pins 2 ring o subscriber loop connection ring 3 tip o subscriber loop connection tip interface pins to qap 7 c1 i/o ternary logic input, controlling the operation mode; in case of thermal overload this pin sinks a current of typ. 150 a 8 c2 i ternary logic input, controlling the operation mode 20 c3 i binary logic input, controlling the operation mode; can be non connected if not used
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 29 2000.07.06 preliminary 12,13 dcp,dcn i differential two wire dc-input voltage; multiplied by factor ? 25 and related to (vh ? vbat) / 2, dcn appears at tip and dcp at ring output, respectively 14,15 acp,acn i differential two wire ac-input voltage; multiplied by factor ? 3.125, acn appears at tip and acp at ring output, respectively 18 it o current output representing the transversal current scaled down by a factor of 50. 19 il o current output: longitudinal line current scaled down by a factor of 50. miscellaneous 9 supfi o reference voltage defining the common mode line potential. an external capacitance together with the internal 30 k ? resistance enables supply voltage filtering. pin no. symbol type description
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 30 2000.07.06 preliminary 1.4.4 functional block diagram (peb 4166/4) figure 9 functional block diagram (peb 4166/4) tip ib ia bandgap logic sensor (ia + ib) / 100 it 50k 50k 16k 16k 2k supfi acp c1 vh 2k (ia - ib) / 100 vh' vh' vh' bgnd dcp dcn acn off hook sensor switch il + + - - symfi vh' vh' agnd vdd(+5v) vss(-5v) (vh' +vb') / 58,25 ring 5k bgnd pdnr or c3=1 vbat switch vb' vbat2 vb' vb' c3 c2 5k 8v ezm07105.emf
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 31 2000.07.06 preliminary figure 10 central office analog linecard for 16 subscribers ezm07118.emf peb 31666 peb 31664 mupp c peb 3465 qap t/r pcm p-mqfp-64-1 p-mqfp-80-1 p-dso-20-5 peb 4166 peb 4164 ahv-slic peb 3465 qap 4 wire 1 16 ahv-slic p-mqfp-80-1 p-dso-20-5 t/r c peb 4166 peb 4164
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 32 2000.07.06 preliminary figure 11 typical application circuit of the muslic chip set ezm07127b.wmf 50 ? 50 ? 18n / 100v bgnd 50 ? 50 ? bgnd tip ring bgnd agnd bgnd agnd supfi ahv slic agnd agnd 680k 1,5k 470n it il acp acn dcp dcn c1 c2 1,5k itac-a vr-a il-a acp-a acn-a dcp-a dcn-a c1-a c2-a it-a io1-a io2-a i1-a o1-a agnd dgnd rref gnd-a gndz gndi qap v dd-a , v ddz reset adcl afsc add adu adr dgnd reset adcl afsc add 1/2 adu 1/2 dgnd 4x680k ? io1 io2 io3 io4 id0 id1 id2 id3 dgnd vss mupp c tca dra dxa pclk tcb drb dxb dgnd a0 a7 dio0 dio7 csq ale wrq rdq intr muxq intq/mot peb 4166 peb 3465 peb 31666 c- interface pcm- highway a pcm- highway b fsc mclk agnd agnd c dcp c dcn 470n agnd v h v bat -5v v h v dd v ss v bat agnd dgnd agnd -5v v ddi v ss v a v b v bim dgnd +3,3v dgnd v dd v dd5 v bat2 v bat2 100n 100n 100n reset 22 100n +3,3v 100n v ddp dgnd 100n v h v bat 3*100n bgnd -5v 2*1 agnd 22f dgnd e.g. stps 160a +5v +5v v bat2 680k 18n / 100v r pt2 r pt1 r pr2 r pr1 c pt c pr 1) 1) this diode (one per linecard) is only necessary if it is not guaranteed that the 5v line is settled before or at the same time as v dd (3.3 v) c itac r it r il r qio c3 r qio c sup +5v +3,3v or +5v +5v +5v
peb 3465, peb 31666/4, peb 4166/4 muslic introduction preliminary data sheet 33 2000.07.06 preliminary for the connection of the ahv-slic and the qap to the mupp ? only one channel is depicted here. table 2 list of components in typical application circuit ( figure 11 ) symbol value unit tolerance min. typ. max. r pt1 1) 1) absolut value not critical, but matching with r pr1 is important. 30 50 ? 0.1 % r pt2 2) 2) absolut value not critical, but matching with r pr2 is important. 050 ? 0.1 % r pr1 30 50 ? 0.1 % r pr2 050 ? 0.1 % r it 1.5 k ? 1% r il 1.5 k ? 1% r qio 680 k ? 5% r mio 680 k ? 5% c pt 0.2 18 20 nf 10 % c pr 0.2 18 20 nf 10 % c itac 470 nf 10 % c dcp/n 100 nf 10 % c sup 470 nf 10 %
peb 3465, peb 31666/4, peb 4166/4 muslic functional description preliminary data sheet 34 2000.07.06 preliminary 2 functional description the multichannel subscriber line interface codec filter chip set, muslic, is a logic continuation of the well established family of the infineon technologies pcm-codec- filter-ics with the integration of all dc-feeding, ringing, supervision and meterpulse injection features on chip as well. fabricated in advanced cmos, bicmos and high voltage technology spt170 the muslic is tailored for very flexible solutions in analog/ digital communication systems. the chip set consists of the digital signal processor for 16 channels (mupp c, multichannel processor for pots), the analog/digital and digital/analog converter for 4 channels (qap, quad analog pots) and the high voltage interface chip for 1 channel (ahv-slic, advanced high voltage subscriber line interface circuit). the mupp ? uses the benefits of a dsp not only for the voice channel but even for line feeding and supervision which leads to a very high flexibility without the need of external components. based on an advanced digital filter concept, the peb 31666 (mupp c) and the peb 3465 (qap) provides excellent transmission performance. the new filter concept leads to a maximum of independence between the different filter blocks. each filter block can be seen as a one to one representative of the corresponding network element. together with the software package muslicos, filter optimizing to different applications can be done in a clear and straight forward procedure. the ac frequency behavior is mainly determined by the digital filters. using the oversampling 1 bit sd-ad/ da converters, linearity is only limited by second order parasitic effects. the digital solution offers free programmability of feeding current and voltage as well as very fast settling of the dc-operating point after transitions. a 0.3 hz lowpass filter in the dc-loop is mainly responsible for the system stability. additionally teletax generation and filtering is implemented as well as free programmable balanced ring generation with zero-crossing injection. off-hook detection with programmable thresholds is possible in all operating modes. to reduce overall power consumption of the linecard, the mupp ?, the qap and the ahv-slic provide a power down mode. to program the muslic or to get status information about the chip set or the system the muslic has a 8-bit-parallel simple microcontroller interface. the ahv-slic-e peb4166 provides battery feeding between ? 15 v and ? 80 v and ringing injection with a differential ring voltage up to 85 vrms. in order to achieve these high amplitudes, an auxiliary positive battery voltage is used during ringing. this voltage can also be applied to drive very long telephone lines. the ahv-slic-s peb4164 does not support this auxiliary positive voltage. a kind of power management can be performed by using a second battery supply voltage for power saving at short lines.
peb 3465, peb 31666/4, peb 4166/4 muslic functional description preliminary data sheet 35 2000.07.06 preliminary the ahv-slic is designed for a voltage feeding - current sensing line interface concept and provides sensing of transversal and longitudinal currents on both wires. in power down mode the ahv-slic is switched off turning the line outputs to a high impedance state. off-hook supervision is provided by activating a line current sensor.
peb 3465, peb 31666/4, peb 4166/4 muslic functional description preliminary data sheet 36 2000.07.06 preliminary 2.1 principles 2.1.1 signal flow graph: ac figure 12 signal flow graph: ac transmit path the analog input signal has to be connected to pin itac of the peb 3465 by an external capacitor (470 nf) for ac/dc separation. after passing a programmable gain stage (agx = 0, 3.5 or 9.5 db, digitally compensated) and a simple antialiasing prefilter the voice signal is converted to a 1-bit digital data stream in the ? -converter. the first down sampling steps are done in fast running digital hardware filters on the peb 3465. this down sampled ac-signal (64 khz sampling rate) is sent to the mupp ? via the mupp c/qap-interface in the adu-channel. the following signal processing is done in the dsp-machine of the mupp ?. the benefits of this are the programmability of frequency and gain behavior. at the end the fully processed signal is transferred to the pcm interface in a pcm-compressed (a-law / ?law) signal representation. peb 31666 / peb 31664 peb 3465 agx adc im2 imfix1 agr dac aim im1 imfix2 int dez xfix1 frx ax1 cmp ar2 rfix2 ttx- gen. xfix2 ttx- filter x1 ax2 rfix1 frr ar1 exp th thfix + + + itac acp, acn pcm output pcm input dhpr dhpx tg1 tg2 receive path transmit path functional block user programmable block fixed filter block only in peb 31666 ezm07108.emf
peb 3465, peb 31666/4, peb 4166/4 muslic functional description preliminary data sheet 37 2000.07.06 preliminary receive path the digital input signal is received via the pcm interface of the mupp ?. expansion, pcm-lowpass-filtering, gain correction and frequency response correction are the next steps which are done by the dsp-machine. this 64 khz ac signal is sent from the mupp c to the qap via the mupp c/qap-interface in the add-channel. the up sampling interpolation steps are processed by fast hardware structures in the peb 3465 to reduce the dsp-workload. the 1-bit data stream is then converted to an analog equivalent. a subsequent programmable gain stage (agr = 0 or ? 3,5 db) and smoothing filter provides the ac output signal at the pins acp and acn of the peb 3465 for direct connection to the ahv-slic. loops there are two different loops implemented: the impedance matching (im) loop which is divided into 3 separate loops to guarantee very high flexibility to various impedances, and the transhybrid balancing (th) loop. 2.1.2 signal flow graph: dc figure 13 signal flow graph: dc user programmable block functional block fixed filter block it dcp, dcn pcm input pcm output adc dec. ag dcr dac int. ag dcx peb3465 peb31666 / peb 31664 lpo3 dcchar lpo5 rng ramp not available in peb31664 levelmeter unit ezm07109.emf
peb 3465, peb 31666/4, peb 4166/4 muslic functional description preliminary data sheet 38 2000.07.06 preliminary dc characteristic the incoming information (transmit direction) at pin it (scaled transversal ac + dc- current, transferred to a voltage via an external 1.5 k ? resistor at it) passes first a antialiasing filter and is then converted to a 1-bit digital data stream in the = ? -converter. down sampling is done in hardware filters of the peb 3465. this dc-information (2 khz sampling rate) is then fed to the mupp c where it is first lowpass filtered (0.3 hz corner frequency) for stability and noise reasons. the following dc-characteristic consists of three branches which represents different kinds of feeding behavior. in typical applications it acts as a programmable constant current source ( r i >30k ? ). if the desired value cannot be held feeding switches automatically and smoothly to the resistive branch at v lim . the internal resitance in this range is programmable between 0 and 1.6kohm (external fuse resistors not included). in the third branch the dc- characteristic switches to a constant voltage behavior. in this area the slope of the dc- characteristic is determined by the external fuse resistors. for superimposing voice as well as teletax pulses the necessary drop at the line can be calculated and taken into account as well. the outgoing bit stream (2 khz sampling rate), representing the dc- feeding value is then sent back to the peb 3465 where a 1-bit ? -converter and a following smoothing filter (using 2* 100nf external capacitors) establish the desired values at the pins dcp and dcn, respectively. depending on the operating mode (active, ringing, active with boosted battery) a gain of 0 or 4 db is inserted. figure 14 dc characteristic in normal battery mode v lim v const v bat v tip/ring r fuse r fs r i constant current feeding range resistive feeding range constant voltage feeding i tip/ring peb31666_0002_dc-charactreistics
peb 3465, peb 31666/4, peb 4166/4 muslic functional description preliminary data sheet 39 2000.07.06 preliminary supervision the hook-information is the most important one and is provided via the ?-interface (scr8-4: hook; see page 82 ), in all operating modes: power down: in this state the transversal line current is sensed by the ahv-slic and fed to the peb 3465 via pin it. off-hook is detected if the voltage at it exceeds a programmed value. active: off-hook is detected if the incoming voltage at it exceeds a programmed value. to avoid instable information, lowpass filtering and a hysteresis is provided. ringing: off-hook is detected if the dc-value at it exceeds the programmed ring trip threshold. the ac-value is filtered automatically. ring trip detection is reported within 2 cycles of the ring period and then the internal ring generator is switched off within 2 cycles at zero crossing of the ring voltage. for ground key information the ahv-slic provides the longitudinal current information at the pin il. the peb 3465 uses a ? -converter - similar to the dc-transmit path - to convert this signal to its digital representation. the accuracy is + 8% compared to + 5% of the dc-path. the 1-bit digital data stream is also down sampled and sent to the mupp c via the adu-channel of the mupp ?/qap-interface. generation of the ground key bit is done in the mupp ? (scr8-3: gnk; see page 82 ) additional features the peb 3465 provides three general purpose input pins (va, vb, vbim) for measuring. via the mupp c/qap-interface it is possible to select one of these inputs for the measurement. the dc-signal at the selected input is converted to digital using the same ? -converter as for ground key information (accuracy of + 8%) and sent to the mupp ?. the input range is between ? 2.4 v ? + 2.4 v. as a further selection it is also possible to measure the internal vddz-voltage of the peb 3465. this voltage is internal divided by 4 and can be measured by setting vddim. 2.1.3 ahv-slic the advanced high voltage subscriber line ic's peb4166 / peb4164 are reliable interfaces between the telephone line and the qap/mupp. the ahv-slic supports ac and dc control loops based on feeding a voltage v tr to the line and sensing the transversal line current i trans (see figure 15 ). dc- and ac-voltages are handled separately with different gain on the ahv-slic. both are applied differentially via pins dcp, dcn, and acp, acn, respectively. the line voltages v r and v t are the amplified input voltages, related to the mean supply voltage.
peb 3465, peb 31666/4, peb 4166/4 muslic functional description preliminary data sheet 40 2000.07.06 preliminary v t = v tip = ( v h ? + v b ? ) / 2 ? 25 v dcn ? 50/16 v acn v r = v ring = ( v h ? + v b ? ) / 2 ? 25 v dcp ? 50/16 v acp . note: active mode: v h ? =0, v b ? = v bat boosted battery mode: v h ?= v h ?2v, v b ? = v bat 1) active2 mode: v h ? =0, v b ?= v bat2 the transversal line voltage v tr = v t ? v r is simply related to the input voltages: v tr = 25 ( v dcp ? v dcn ) + 50/16 ( v acp ? v acn ) = 50 v dcp + 6.25 v acp a reversed polarity of v tr is easily obtained by changing the sign of ( v dcp ? v dcn ). scaled images of the transversal and longitudinal currents are measured and provided at the it and il pin, respectively: i it = ( i t + i r )/100 = i trans /50 i il = ( i t ? i r )/100= = i long /50 figure 15 definition of output current directions 1) for the ahv-slic-s (peb 4164) vh = vdd = 5v buffer v tr z l 2 z l 2 i long i long i r i t ring tip i trans buffer i trans = ( i t + i r )/2 i long = ( i t ? i r )/2 ezm07110.emf
peb 3465, peb 31666/4, peb 4166/4 muslic functional description preliminary data sheet 41 2000.07.06 preliminary 2.1.3.1 operating modes the ahv-slic operates in different modes controlled by ternary logic signals at the c1 and c2 input and the binary logic signal at the c3 input (see table 3 and table 4 ). pdnh........ power down high impedance pdnr........ power down resistive pdnr-l .... power down resistive-load act........... active mode act2......... active mode using vbat2 bb-50........ boosted battery with min. 50 ma current limitation hir............ ring wire set to high impedance hit ............ tip wire set to high impedance hirt ......... ring and tip wires set to high impedance note: note: the ?-r? suffix in table 4 means that there is an internal 5 k ? connection between tip and gnd and also between ring and vbat. bb-100 .......boosted battery with min. 90 ma current limitation (without 5k ?) the power down (pdn) states are intended to reduce power consumption of the linecard to a minimum: the ahv-slic is switched off completely, no operation except off-hook supervision is available. table 3 programming of operating modes (pin c3 = 0 v or open) c3 = 0v or open c2 (pin 8) vil vim vih c1 (pin 7) vil pdnr-l pdnr hir vim pdnh bb-50 hit vih act2 act hirt table 4 programming of operating modes (pin c3 = 5 v) c3 = 5 v c2 (pin 8) vil vim vih c1 (pin 7) vil pdnr-l pdnr hir-r vim pdnh-r bb-100 hit-r vih act2-r act-r hirt-r
peb 3465, peb 31666/4, peb 4166/4 muslic functional description preliminary data sheet 42 2000.07.06 preliminary with respect to the output impedance of tip and ring three pdn-modes have to be distinguished: ? the pdnr (power down resistive) mode provides a connection of 5 k ? each from tip to bgnd and ring to vbat, respectively, while the outputs of the buffers show high impedance. the current through these resistors is sensed, 1/10 is transferred to the it pin to allow off-hook supervision. ? the pdnh (power down high impedance) mode offers high impedance at tip and ring. ? the power down resistive - load (pdnr-l) state is automatically activated for a duration of 2 ms on any power down mode to any active mode transition. the function is to preload the supfi capacitor in order to suppress line voltage transients. active (act): this is the regular transmit and receive mode for voiceband and teletax. the line driving section is operated between vbat and bgnd. active2 (act2): this is the regular transmit and receive mode for voiceband and teletax in which the reduced battery voltage vbat2 is used (allows power saving at short lines). the line driving section is operated between vbat2 and bgnd. boosted battery (bb) 1) : in order to provide a balanced ring signal of up to 85 vrms or to drive longer telephone lines, an auxiliary positive battery voltage vh is used, enabling a higher voltage across the line. transmission performance remains unchanged compared with act mode. high impedance (hir/hit/hirt) 1) : in this mode each of the line outputs can be programmed to show high impedance. hit switches off the tip buffer, while the current through the ring output still can be measured by it or il. programming hir switches off the ring buffer. in the mode hirt both buffers show high impedance. 2.1.3.2 current limitation / overtemperature in any operating mode except pdn the total current in the buffer output stages is limited to a maximum value of typically 100 ma. (exception modes with suffix "- 50") if, however, the junction temperature exceeds 165 c (typ.), the buffers are switched off completely; switching on again occurs with a hysteresis of 20 c, i.e. at t j = 145 c. besides, for signalling overtemperature, the ahv-slic drains a current i ot from pin c1. this current is sensed by the qap and transferred in the adu channel to the mupp ?. the mupp c generates an interrupt signal on the ? interface, where the overtemperature condition can be identified by reading the interrupt register, scr8 and tcr0. 1) not possible together with peb 4164
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 43 2000.07.06 preliminary 3 interfaces 3.1 pcm interface two serial pcm-interfaces are used for the transfer voice data. the pcm-interface consist of 8 pins: the frame sync (fsc) pulse identifies the beginning of a receive and transmit frame for all of the 16 channels. the pclk clock is the signal to synchronize the data transfer on both lines dxa (dxb) and dra (drb). bytes in all channels are serialized to 8 bit width and msb first. as a default setting, the rising edge indicates the start of the bit, while the falling edge is used to latch the contents of the received data on dra (drb). if the double clock rate is chosen (twice the transmission rate) the first rising edge indicates the start of a bit, while the second falling edge is used for latching the contents of the data line dra (drb) by default. the data rate of the interface can vary from 2*512 kb/s to 2*8192 kb/s (2 highways) a frame may consist of up to 128 time slots of 8 bits each. in the time slot configuration registers scr6 and scr7 the user can select an individual time slot, and an individual pcm-highway, for any of the 16 voice channels. receive and transmit time slots can be programmed individually in normal mode (pcm) and in linear mode. an extra delay of up to 7 clocks, valid for all channels, as well as the sampling slope may be programmed (see register xr6). when the mupp c is transmitting data on dxa (dxb), pin tca (tcb) is activated to control an extra external driving device. pclk: pcm-clock, 512 khz to 8192 khz fsc: frame synchronization clock, 8 khz dra: receive data input for pcm-highway a drb: receive data input for pcm-highway b dxa: transmit data output for pcm-highway a dxb: transmit data output for pcm-highway b tca: transmit control output for pcm-highway a, active low during transmission tcb: transmit control output for pcm-highway b, active low during transmission
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 44 2000.07.06 preliminary the following table shows possible examples for the pcm-interface, other frequencies like 768 khz or 1536 khz are also possible. figure 16 example for single clock rate, 512 kb/s table 5 pcm interface examples frequency [khz] single/double [1/2] time slots [per highway] datarate [kbit/s per highway] 512 1 8 512 1024 2 8 512 1024 1 16 1024 2048 2 16 1024 2048 1 32 2048 4096 2 32 2048 4096 1 64 4096 8192 2 64 4096 8192 1 128 8192 formula f 1 f/64 f formula f 2 f/128 f/2 3 654 72 10 3 654 7210 125 s voice 0,8 fsc pclk dra,drb dxa,dxb 0 76 3 654 7 210 3 654 7210 0 76 3 654 72103 654 7210 voice 6,14 0 76 3 65 4 7 2 10 3 654 72 1 0 0 76 voice 1,9 voice 7,15 tca,tcb
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 45 2000.07.06 preliminary figure 17 example for double clock rate, 512 kb/s 3 654 72 10 3 654 7210 125 s voice 0,8 fsc pclk dra,drb dxa,dxb 0 76 3 654 7 210 3 654 7210 0 76 3 654 72103 654 7210 0 76 3 6 5 4 7 2 10 3 654 72 1 0 0 76 voice 7,15 tca,tcb voice 1,9 voice 6,14
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 46 2000.07.06 preliminary figure 18 2048 kb/s, single clock operation, only highway a used figure 19 detail a in figure 18 for special purposes the dra/b and dxa/b pins may be strapped together, and form bi-directional data- ? pin ? (like sip with the sld-bus). 0123 time-slot 31 time-slot high 'z' high 'z' 125 s detail a fsc pclk dr1 dx1 tc1 ezm07259.emf fsc pclk dr1 dx1 tc1 voice data voice data high 'z' high 'z' 01234567 76543210 clock bit ezm07260.emf
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 47 2000.07.06 preliminary figure 20 pcm-group delay transmit the group delay of the voice has 1 fsc (in average). figure 20 shows the conditions for the minimum and maximum group delay. in the minimum the group delay is almost 0, whereas in the maximum the delay will be almost 2 fsc ? s ( 250 sec). v0 v7 v6 v5 v4 v3 v2 v1 compander pcm 125 s 125 s v7 v0 v6 v max minimum group delay v0 v7 v6 v5 v4 v3 v2 v1 125 s 125 s v8 v0 maximum group delay v max v2 v4 v max depends on pclk (8..128 time slots per highway) v i ...voice time slots ezm16001.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 48 2000.07.06 preliminary figure 21 pcm-group delay receive the group delay of the voice has 1 fsc (in average). figure 21 shows the conditions for the minimum and maximum group delay. in the minimum the group delay is almost 0, whereas in the maximum the delay will be almost 2 fsc ? s ( 250 sec). v7 v0 v6 pcm expander 125 s 125 s minimum group delay v0 v7 v6 v5 v4 v3 v2 v1 125 s 125 s v8 v0 maximum group delay v max v2 v4 v max depends on pclk (8..128 time slots per highway) v i ...voice time slots v max v0 v7 v6 v5 v4 v3 v2 v1 ezm16002.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 49 2000.07.06 preliminary 3.2 c interface the parallel c-interface is used to communicate with an external master device and consists of six control lines (ale/dsq, csq, rdq/rw, wrq, demux/muxq, intq/ mot), 8 bidirectional address/data lines (dio0 ? dio7) and 8 address-lines (a0 ... a7) and provides fast parallel data transfer to a microcontroller device (intel compatible and motorola compatible families). the ?-interface of the mupp ? has a multiplexed / non multiplexed 8-bit address/data bus and allows direct connection to a microcontroller of the intel 8051-(mcs51/251-) family, the infineon technologies c16x-family and motorola m68hcxx 1) or m683xx 1) family without additional components. intel / infineon technologies family: intel multiplexed mode: muxq/demux = 0 intq/mot = 0 intr active high with each falling edge of ale-line the mupp c latches the bus data on the 8 data lines dio0...dio7 and stores it as an address information. csq combined with rdq or wrq starts the data transfer cycle via the parallel ?-interface. if csq is low, the data on dio0...dio7 will be valid on the rising edge of wrq/rdq. depending on the previously latched address information, these data have a different meaning. in case of a reset command for the ?-interface the address information 0000 0011 has to be sent together with the data information 1010 1010. data transfer to and from the muslic is asynchron and the data will be transferred in bytes. intel demultiplexed mode: muxq/demux = 1 intq/mot = 0 intr active high in intel demultiplexed mode, the address- and the data-information is given on separate bus lines a0... a7 and dio0...dio7. every falling edge of the ale-line latches the address information. csq combined with rdq or wrq starts the data transfer cycle in the same way as in the multiplexed mode. 1) information is preliminary
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 50 2000.07.06 preliminary motorola demultiplexed mode muxq/demux = x (don ? t care) intq/mot = 1 intr active low in motorola mode address information and data information are given on separate bus lines (a0 ... a7, dio0 ... dio7). the address information has to be valid before rdq/ rwq and ale/dsq are indicating a read- or write-cycle. the data information is latched by the rising edge of the ale/dsq signal. table 6 possible address information to identify the following data nibbles address command function 00000000, 00h channel preselection of channel for channel specifc commands sop, top, copi 00000001, 01h status status register to control the read/ write-operations 00000010, 02h interrupt register (read only) indicates channel and sources of pending interrupts 00000011, 03h reset reset of the ? interface by write of data 0aah to this address 00000100, 04h reserved 00000101, 05h interrupt channel reg. 1 indication of pending interrupts on channel 0..7 00000110, 06h interrupt channel reg. 2 indication of pending interrupts on channel 8..15 00000111, 07h data data port for all register read/write- operations 00001100, 0ch version register when read, indicates the version of the mupp ? device in hexadecimal representation. value returned by current version = 13h
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 51 2000.07.06 preliminary status register the status register controls the data transfer between mupp and the system via the c interface. note: a read operation of the status register resets all bits which are set at this time. bit76543210 0 0 0 0 chksum _rdy sample _rdy du_rdy dd_rdy chksum_rdy checksum ready; after start of the checksum generation by the xop command this bit indicates the status of the checksum generation chksum_rdy = 0 checksum generation in progress chksum_rdy = 1 checksum generation finished sample_rdy 1) 1) for peb 31664 this bit has to be ignored sample ready; indicates that a new sample result is available in scr4/5. reading of sample results should be implemented according to flow chart figure 22 . sample_rdy = 0 no new sample result is available. sample_rdy = 1 new sample result is available (bit sample_rdy is reset by status register read operation). du_rdy data upstream ready; indicates that valid data are aviable for a read command du_rdy = 0 read data not valid du_rdy = 1 read data valid dd_rdy data downstream ready; indicates that a write operation (e. g. broadcast, block transfer) is finished dd_rdy = 0 write operation still in progress dd_rdy = 1 write operation finished
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 52 2000.07.06 preliminary figure 22 reading of sample results peb31666_0000_sample.emf end begin read scr4 read status register sample_rdy = 0 scr4/5 values not consistent scr4/5 values are consistent command sop read scr4 read status register du_rdy = 0 du_rdy = 1 read scr5 command sop read scr5 read status register du_rdy = 0 du_rdy = 1 read status register sample_rdy = 1 sample_rdy = 1 sample_rdy = 1 end begin read scr4 read status register sample_rdy = 0 scr4/5 values not consistent scr4/5 values are consistent command sop read scr4 read scr5 command sop read scr5 read status register sample_rdy = 1 wait 2us wait 2us sample_rdy = 1 sample_rdy = 1 status register polling: guaranteed command recovery time:
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 53 2000.07.06 preliminary 3.2.1 interrupt sequence description: all of the 6 scr8 bits (qio2, qio1, qi1, hook, gnk, slcx) can generate an interrupt. all of the scr8 bits can be masked to prevent the generation of an interrupt with the mask-register (except slcx). behind slcx there are more additional interrupt bits (described in chapter 4.1.3 at page 109 ). each of these bits which set the slcx bit can be masked with the scr2 register (except the res bit). each of the 16 channel has its own scr8-register. these registers can be read via the c-interface (sop command). the 2 lsb of the scr8-register are not defined yet. the interrupt channel registers indicate a pending interrupt in the corresponding channel. all 30 ? one channel will be handled and the corresponding interrupt channel register is set if an interrupt has occured. all 500 s the interrupt channel registers will be updated. information of the interrupt channel registers is reset by reading them. figure 23 interrupt sequence interrupt register: c3 s3 c1 c2 c0 s2 s1 s0 . . channel 0 channel 15 500 us scr8: qio2 qio1 qi1 hook gnk slcx tbd tbd channel 0 channel 15 qio2 qio1 qi1 hook gnk slcx tbd tbd intr . . . . . . . scr8: qio2 qio1 qi1 hook gnk slcx tbd tbd qio2 qio1 qi1 hook gnk slcx tbd tbd scr9 (mask- register) #7 #6 #5 #4 #3 #2 #1 #0 interrupt channel reg. 1 #15 #14 #13 #12 #11 #10 #9 #8 interrupt channel reg. 2 scr8: scr9 (mask- register) scr8: ezm07111.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 54 2000.07.06 preliminary 3.2.2 interrupt handling simple case: only one interrupt occurs: in this case it is very simple to get the ir source. the information is stored in the interrupt register. this register contains the channel-number in the 4 msb and the source in the 4 lsb. reading this register all information is available. but in the case of slcx-interrupt the tcr0 register has to be read next to get the additional interrupt source. if no interrupt is pending, the interrupt register is responding the value 08h (see "idle (no interrupt)" in table 7 ). since it is not allowed to interrupt a data command (address 7 read/write) care must be taken, that data port access sequences resulting from normal command operations are not interrupted by access of the interrupt service routine. table 7 interrupt register interrupt register c3 c2 c1 c0 s3 s2 s1 s0 channel 0 0 0 0 0 . . . channel 15 1 1 1 1 slcx 0000 gnk 0001 hook 0010 qi1 0011 qio1 0100 qio2 0101 more than 1 interrupt 0 1 1 1 more than 1 channel 1 1 1 1 idle (no interrupt) 0 0 0 0 1 0 0 0
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 55 2000.07.06 preliminary case: more than one interrupt was generated: if more than one interrupt per channel occurs, the source bits (s3 ... s0) are set to 0111. the channel information in the interrupt register is valid and the interrupt source can be read from scr8. interrupts in different channels generate 1111 in the source bits (s3 ... s0). in this case the channel information is not valid, because the interrupt register will be updated with each interrupt. in this case all scr8-registers must be read. ? general: slcx-interrupt: in the case that one bit of the tcr0-register ist set, all other tcr0-bits cannot be modified as long as the tcr0-register is not read. after reading this register slcx will be reset to 0 but not before two 8 khz frames.
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 56 2000.07.06 preliminary 3.3 mupp c/qap interface the mupp c/qap-interface, the link between the mupp ? and the qap, is a serial interface based on the 6 signals afsc (analog frame sync), adcl (analog data clock), adu1/adu2 (analog data upstream) and add1/add2 (analog data downstream). adu1 and add1 are common to the first group of 8 time slots (channels) and adu2 and add2 to the second 8 time slots (channels). afsc and adcl are common to both groups of time slots. figure 24 mupp c/qap interface: frame, bit structure 012 31 30 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 . . . . . . . . 012 31 30 ch 8 ch 9 ch 14 ch 15 . . . . . . . . 0 12 31 30 dc, control 17 18 19 20 afsc add1/adu1 (slot group 1) add2/adu2 (slot group 2) 15.625 s (64 khz) 500 s (2 khz) 1.95 s (512 khz) ac (voice, data) 61ns (16.384mhz) ezm07129.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 57 2000.07.06 preliminary figure 25 interrupt handling (first step) read interrupt register freeze interrupt channel registers and activate channel shadow registers write 08h to interrupt register (setting interrupt inactive) intr pin inactive interrupt register s3 - s0 = f (more than 1 channel) read interrupt channel registers 1 and 2 reset channel register, copy shadow to channel register, switch shadow register transparent b a this sequence cannot be interrupted. external updates are delayed. intr pin inactive if new interrupts are occured, intr pin active yes no reset channel register, copy shadow to channel register, switch shadow register transparent 14 15 0 8 1 9 2 10 3 11 4 12 5 13 6 14 7 15 0 1 channel t 2khz user action mupp c internal action interrupt pin active ezm36008.emf
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 58 2000.07.06 preliminary figure 26 interrupt handling (second step - interrupts in one channel) read scr8 of channel c0 - c3 compare with previous scr8 to identify changes read tcr0 compare tcr0 with previous tcr0 to identify changes s0 - s3 < 7 (only one interrupt) ** process interrupts process interrupt e a slcx interrupt? process interrupt(s) s0 - s3 = 0 (slcx interrupt) no yes yes no yes no ** or, if the interrupt cannot be serviced within 500 s, scr8 has to be read in order to decide if a multiple interrupt occured. ezm36009.emf
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 59 2000.07.06 preliminary figure 27 interrupt handling (second step - interrupts in two or more channels) ezm36010.emf e identify channels with pending interrupts by interrupt channel registers b read scr8 all channels with pending interrupts processed? compare with previous scr8 to identify changes read tcr0 compare tcr0 with previous tcr0 to identify changes process interrupt(s) slcx interrupt? process interrupt(s) yes no select next channel to process interrupts no yes
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 60 2000.07.06 preliminary 3.4 qap/ahv-slic interface output voltage ac (acp, acn) the output voltage at the pins acp and acn represents the ac-information (including teletax signal) at the receive path. the ac-information is received via the mupp ?/ qap-interface in the add channel. the 64-khz bitstream is converted to analog, passes a programmable gain stage of 0 / ? 3.5 db (ttx is also affected) and is buffered to drive a load of r l >15k ? and c l < 20 pf, which is the input impedance of the ahv-slic. output voltage dc (dcp, dcn) the output voltage at the pins dcp and dcn represents the dc-information together with the ring burst at the receive path. the dc-information is received via the mupp ?/ qap-interface in the add channel. the 2-khz bitstream is d/a converted and is lowpass filtered by using two external smoothing capacitors of 2x100 nf. the pins are directly connected to the ahv-slic. transversal current sense ac - input (itac) the pin itac is the input voltage pin for the ac transversal current information from the ahv-slic in the transmit path. ac/dc separation is done by an external highpass filter (ext. capacitor = 470 nf). the input resistance is larger than 20 k ? . current/voltage conversion is performed via an external resistor of 1.5 k ? (same for pin it). the signal passes a programmable gain stage 0, 3.5 or 9.5 db, is converted to digital and sent to the mupp c via the mupp ?/qap-interface in the adu channel (64-khz bitstream). transversal current sense dc - input (it) the pin it is the input voltage pin for the dc transversal current information from the ahv-slic in the transmit path. the input resistance is larger than 500 k ? . current/ voltage conversion is done via an external resistor of 1.5 k ? (same for pin itac). the voltage at pin it is lowpass filtered and converted to digital. the bitstream (2 khz) is sent to the mupp ? via the mupp ?/qap-interface for further signal processing. longitudinal current sense - input (il) the scaled longitudinal current information transferred from the ahv-slic - the current/ voltage conversion is done by an external resistor of 1.5 k ? - is converted into digital and sent to the mupp ? via the mupp c/qap-interface in the adu channel. in the mupp ? the il-information is lowpass filtered (time programmable using dupgnk- counter) and reported via the scr8 (see page 82 ) if the measured value exceeds a programmed limit. in power down, the gnk-bit is set to ? 0 ? and the setting of the interrupt bit (scr8) caused by gnk is prohibited.
peb 3465, peb 31666/4, peb 4166/4 muslic interfaces preliminary data sheet 61 2000.07.06 preliminary control interface (c1, c2, c3) in order to set the ahv-slic to different operating modes, the information of the board controller is passed through from the ?-interface to the ternary ahv-slic interface pins c1, c2 and the binary interface pin c3 (see chapter 2.1.3.1 ). it is recommended to connect the resp. io-2 pin of the qap to drive the resp. c3 pin of the ahv-slic (see table 3 and table 4 in chapter 2.1.3.1 ). for signalling ? over temperature ? the ahv-slic drains a current (i ot ) from pin c1. this current is sensed by the peb 3465 and transferred in the adu channel to the mupp ?. the mupp c sends the overtemperature message via the scr8 (slcx) and tcr0-5 to the ? interface. this is possible in any operating states of the ahv-slic interface except for power down.
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 62 2000.07.06 preliminary 4 programming the muslic with the appropriate commands, the muslic can be programmed by the microcontroller interface. data transfer to and from the muslic is asynchron and the data will be transferred in bytes. (for more information, about the ? interface see chapter 3.2 ).
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 63 2000.07.06 preliminary 4.1 types of c interface bytes the ? interface bytes have to be interpreted as either commands or status information stored in configuration registers or the coefficient rams. there are 5 different types of muslic commands which are selected by bit 4 and 5 (partly bit 2 and 3) as shown below. sop status operation: muslic status setting/monitoring xop extended operation: general settings top transfer operation: read certain status/options only cop coefficient operation: filter coefficient setting/monitoring copi coefficient operation initialize: coefficient set assignment bit76543210 b rw 0 1 lsel3 lsel2 lsel1 lsel0 bit76543210 0 rw 1 0 lsel3 lsel2 lsel1 lsel0 bit76543210 0r1100lsel1lsel0 bit76543210 icram rw 0 0 0 1 wcram1 wcram0 bit76543210 brw0010lsel1lsel0
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 64 2000.07.06 preliminary table 8 storage of programming information 13 status configuration registers: (for each channel) scr0, ? scr10 accessed by sop command 2 test registers: (for each channel) stcr0, stcr1 accessed by sop command 10 extended configuration registers: xr0 ? xr9 accessed by xop command 19 extended test registers: xtr0 ? xtr18 accessed by xop command 2 transfer configuration registers: (for each channel) tcr0, tcr1 accessed by top command ac- and dc-coefficient rams: crams accessed by cop command 2 coefficient set assignment registers: (for each channel) car0, car1 accessed by copi command
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 65 2000.07.06 preliminary overview of commands and registers via the c interface: sop command bit 7 6 5 4 3 2 1 0 sop for scr/stcr b rw 0 1 lsel3 lsel2 lsel1 lsel0 sop configuration registers bit 7 6 5 4 3 2 1 0 scr0 polnr n/bb lb etg2 etg1 eno ente cor scr1 ttxno ttx12 nosl sorev swdcc act2 qio2d qio1d scr2 vb/2m iconm tempm failm mvam lsupm 1 1 scr3 ag6db lin law cor8 pcmon modem usgain aim scr4 low byte of dc-offset compensation scr5 high byte of dc-offset compensation scr6a r-way rs6 rs5 rs4 rs3 rs2 rs1 rs0 scr6b r-way rs6 rs5 rs4 rs3 rs2 rs1 rs0 scr7a x-way xs6 xs5 xs4 xs3 xs2 xs1 xs0
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 66 2000.07.06 preliminary scr7b x-way xs6 xs5 xs4 xs3 xs2 xs1 xs0 scr8 qio2 qio1 qi1 hook gnk slcx 0 0 scr9 qio2m qio1m qi1m hookm gnkm 1 1 1 scr10 qio2 qio1 qo1 m2 m1 m0 0 0 stcr0 fuse3 fuse2 fuse1 fuse0 0 0 0 0 stcr1 rsv5 rsv4 rsv3 rsv2 rsv1 rsv0 0 0 note: = differences between muslic-e and muslic-s; for details see register description xop command bit 7 6 5 4 3 2 1 0 xop for xr/xtr 0 rw 1 0 lsel3 lsel2 lsel1 lsel0 xop configuration registers bit 7 6 5 4 3 2 1 0 xr0 mio4d mio3d mio2d mio1d mio4 mio3 mio2 mio1 xr1 dupgnk dup
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 67 2000.07.06 preliminary xr2 rexten crsh_a crsh_b fixc idr ex-mclk fix-chan 0 xr3 low byte of ac-cram checksum xr4 high byte of ac-cram checksum xr5 low byte of dc-cram checksum xr6 high byte of dc-cram checksum xr7 ecic1 (byte 0 to byte 14) xr8 ecic2 (byte 15 to byte 29) xr9 c-mode c-s r-s drv_0 shift pcm-offset
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 68 2000.07.06 preliminary xop test register 1 bit 7 6 5 4 3 2 1 0 xtr0 hit hir elm softon opim8m dlp03 dlp5 dispofi xtr1 cal lmsel1 lmsel0 lmnotch lmbp lm2pcm pcm2dc itime xtr2 ring-on ddcc dcad16 eramp erect ac-adcpd ac-dacpd afe-off xtr3 dhp-x dhp-r th frx frr ax ar im xtr4 dlb-8m dlb-64k dlb-32k dlb-pcm alb-8m 0 0 dchold xtr5 dc-dlb dc-albit 0 dc-albil dc-albv dclmu2 dclmu1 dclmu0 xtr6 ttxl gainbb noagc ilitmux cot16 ditoff axg0 arg0 xtr7 qdetq4 qdetq3 qdetq2 qdetq1 0 0 calmux1 calmux0 xtr8 0 0 0 0 0 0 0 enrsv xtr9 0 fuse 0 qap 1 fuse 0 qap 2 fuse 0 qap 3 fuse 0 qap 4 xtr10 fuse 1 qap 1 fuse 1 qap 2 fuse 1 qap 3 fuse 1 qap 4 fuse 2 qap 1 fuse 2 qap 2 fuse 2 qap 3 fuse 2 qap 4 xtr11 fuse 3 qap 1 fuse 3 qap 2 fuse 3 qap 3 fuse 3 qap 4 fuse 4 qap 1 fuse 4 qap 2 fuse 4 qap 3 fuse 4 qap 4
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 69 2000.07.06 preliminary xtr12 blocktest 1 xtr13 blocktest 2 xtr14 blocktest 3 xtr15 rsv1q3 rsv1q2 rsv1q1 rsv1q0 rsv2q3 rsv2q2 rsv2q1 rsv2q0 xtr16 rsv3q3 rsv3q2 rsv3q1 rsv3q0 rsv4q3 rsv4q2 rsv4q1 rsv4q0 xtr17 rsv5q3 rsv5q2 rsv5q1 rsv5q0 rsv6q3 rsv6q2 rsv6q1 rsv6q0 xtr1800000000 1) come only into effect for specified channel when bit ente (scro, bit1) is set. therefore, programming the xtr registers with mupp ?- s is not possible
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 70 2000.07.06 preliminary top command bit 7 6 5 4 3 2 1 0 0 r 1 1 0 0 lsel1 lsel0 top configuration registers bit 7 6 5 4 3 2 1 0 tcr0 vb/2 icon temp fail mva lsup res 0 tcr1 nmvb/2 nmicon nmtemp nmfail nmmva nmlsup rlm1 rlm0 cop command bit 7 6 5 4 3 2 1 0 icram rw 0 0 0 1 wcram1 wcram0 set2 set1 set0 code4 code3 code2 code1 code0 copi command bit 7 6 5 4 3 2 1 0 b rw 0 0 1 0 lsel1 lsel0 car coefficient set assignment registers bit 7 6 5 4 3 2 1 0 car0 dc1 dc0 ac2 ac1 ac0 0 0 hload car1 tg1.2 tg1.1 tg1.0 tg2.2 tg2.1 tg2.0 0 0
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 71 2000.07.06 preliminary 4.1.1 sop command to modify or evaluate the muslic status, individually for each channel, the contents of up to 13 configuration registers scr0, ? scr10 may be transferred to or from the muslic. this is done by a sop command (status operation command). bit76543210 b rw 0 1 lsel3 lsel2 lsel1 lsel0 b broadcast b = 0 only one channel (time slot) is programmed b = 1 all channels (up to 16) are programmed with the same information rw read/write information: enables reading from the muslic or writing information to the muslic rw = 0 write to the muslic rw = 1 read from the muslic lsel length select information this field identifies the selected sop register(s) lsel 3 lsel 2 lsel 1 lsel 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 scr0 scr1 scr2 scr3 1) scr4 scr5 scr6a, scr6b scr7a, scr7b scr8 scr9 scr10 scr0 to scr5 stcr0 stcr1 1) the broadcast function for programming all channels with the same information is not available for register scr3.
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 72 2000.07.06 preliminary scr0 configuration register 0 configuration register scr0 defines the basic feeding modes of the muslic and enables/disables test features: reset value: 00 h bit 76543210 polnr n/bb lb etg2 etg1 eno ente cor note: = different meaning for mupp c-s and mupp c-e polnr normal or reverse polarity (see chapter 5.4 ) polnr = 0 sets the muslic to normal polarity feeding polnr = 1 sets the muslic to reverse polarity feeding n/bb muslic-e is in normal or boosted battery mode (see chapter 5.4 ). for muslic-s this bit has to be set to zero n/bb = 0 normal feeding n/bb = 1 changes ternary interface to ahv-slic which sets the ahv- slic to boosted battery mode lb handling of loop back functions for testing pcm loops. lb = 0 normal function lb = 1 peb 31666: the desired loop back function is enabled (selected with xtr4, xtr5); if no loop is selected with xtr4, xtr5 the pcm-loop is switched on peb 31664: pcm-loop is switched on etg2 enables programmable test tone generator 2 etg2 = 0 test tone generator 2 is disabled etg2 = 1 test tone generator 2 is enabled etg1 enables programmable test tone generator 1 etg1 = 0 test tone generator 1 is disabled etg1 = 1 test tone generator 1 is enabled eno muslic-e: enables offset compensation eno = 0 no dc offset compensation eno = 1 dc offset compensation note: for muslic-s this bit has to be set to zero ente muslic-e: enables test. for muslic-s this bit has to be set to zero. ente = 0 normal operation ente = 1 enables the test selected by the test registers (see chapter 7 )
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 73 2000.07.06 preliminary scr1 configuration register 1 configuration register scr1 defines the meterpulse settings and the soft/hard reversal, linear mode and io settings. reset value: 00 h cor cut off receive path for test reasons. this bit cannot be programmed with muslic-s cor = 0 receive path transmission is available cor = 1 receive path is disabled bit76543210 ttxno ttx12 nosl sorev swdcc act2 qio2d qio1d note: = different meaning for mupp c-s and mupp c-e ttxno muslic-e: meterpulses are represented by teletax (ttx) with 12 or 16 khz or with reverse polarity. for muslic-s this bit has to be set to 1. ttxno = 0 meterpulses are represented with 12 khz or 16 khz ttxno = 1 meterpulses are represented with reverse polarity ttx12 muslic-e: teletax-signal with 12 khz or 16 khz ttx12 = 0 16 khz teletax-signal ttx12 = 1 12 khz teletax-signal nosl muslic-e: no slope means that the ramping of teletax (ttx) signal is switched off nosl = 0 slope of ttx-signal is smooth nosl = 1 hard switch of ttx-signal sorev soft reversal meterpulses sorev = 0 hard reversal sorev = 1 soft reversal swdcc switch dc characteristic swdcc = 0 dc standard characteristic swdcc = 1 dc extended characteristic
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 74 2000.07.06 preliminary scr2 configuration register 2 configuration register scr2 is the mask register. each bit of tcr0 (signalling register) can be masked (except the res bit); that means changes of such a 'masked bit' are not causing a change of the slcx - bit (see page 82 , scr8). reset value: ff h act2 active mode with power save status of ahv-slic act2 = 0 normal mode act2 = 1 c1, c2 indicates the power save mode for the ahv-slic in this case the second negative power supply voltage vbat2 at the ahv-slic is used, allows power saving at short lines qio1d direction for programmable io - pin of the qap io1 qio1d = 0 sets the pin io1 as an input qio1d = 1 sets the pin io1 as an output qio2d direction for programmable io - pin of the qap io2 qio2d = 0 sets the pin io2 as an input qio2d = 1 sets the pin io2 as an output bit76543210 vb/2m iconm tempm failm mvam lsupm 1 1 note: = not defined for muslic-s vb/2m mask bit for half battery information vb/2m = 0 each change of the vb/2 bit leads to an interrupt (slcx-bit) vb/2m = 1 changes of vb/2 bit are neglected iconm mask bit for constant current information iconm = 0 each change of the icon bit leads to an interrupt (slcx-bit) iconm = 1 changes of icon bit are neglected tempm mask bit for over temperature information tempm = 0 each change of the temp bit leads to an interrupt (slcx-bit) tempm = 1 changes of temp bit are neglected failm mask bit for clock fail information failm = 0 each change of the fail bit leads to an interrupt (slcx-bit) failm = 1 changes of fail bit are neglected
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 75 2000.07.06 preliminary information about changing half battery- and constant current-information will be neglected on both of the power down and the ringing state. scr3 configuration register 3 reset value: 00 h mvam mask bit for internal measurement results mvam = 0 each change of the mva bit leads to an interrupt (slcx-bit) mvam = 1 changes of the mva bit are neglected lsupm mask bit for line supervision lsupm = 0 each change of the lsup bit leads to an interrupt (slcx-bit) lsupm = 1 changes of the lsup bit are neglected bit 7 6 5 4 3 2 1 0 ag6db lin law cor8 pcmon modem usgain aim ag6db switch for analog gain in receive and transmit (digitally compensated) ag6db = 0 0 db gain ag6db = 1 + 3.5 db gain in transmit, ? 3.5 db gain in receive lin linear mode selection (16 bit linear information in voice channel a (upper byte) and b (lower byte) lin = 0 pcm-mode is selected lin = 1 linear mode is selected law pcm-law selection law = 0 a-law is selected law = 1 -law is selected (255 pcm) cor8 cut off receive (voice only) cor8 = 0 normal operation cor8 = 1 cut off receive is enabled pcmon after reset pcm-highway is switched off (tristate) pcmon = 0 pcm-off (tristate) pcmon = 1 pcm-active
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 76 2000.07.06 preliminary note: the broadcast function realised by a sop command (see chapter 4.1.1 ) for programming all muslic channels with the same information is not available for register scr3 when using the peb 31666 / peb 31664 v1.3 modem this bit changes the roll-off frequency behavior in receive direction. due to a smoother shape of the digital filters higher modem connect rates are possible. modem = 0 normal operation modem = 1 change roll-off frequency behaviour (in compliance with itu-t q.552) usgain this bit enables an additional analog gain of 6 db in transmit direction for improved noise performance. the gain is compensated digitally inside the qap. so there is no coefficient change necessary whether the bit is used or not. care has to be taken due to the fact that the maximum input level is reduced by a factor of 2 (6 db). for an overview about the analog gain combinations possible together with qap v1.2 or higher see table 9 . usgain = 0 normal operation usgain = 1 additional 6 db analog gain; bit has to be set in combination with bit ag6db (register scr3, bit 7). aim this bit enables an analog impedance loop to ensure system stability for input impedances z i > 900 ohms (especially for 1200 ohms or 900 ohms + 2.16 ?). the setting of this bit is calculated within the coefficient software muslicos (version higher than v1.2). (only available together with qap v1.2 or higher, not available together with qap v1.1). aim = 0 normal operation aim = 1 switch on analog impedance loop table 9 analog gain combinations with qap v1.2 or higher bit usgain (scr3, bit 1) bit ag6db (scr3, bit 7) 0 0 normal operation; 0 db analog gain 0 1 3.5 db analog gain in transmit direction ? 3.5 db analog gain in receive direction 1 0 not used 1 1 9.5 db analog gain in transmit direction ? 3.5 db analog gain in receive direction
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 77 2000.07.06 preliminary scr4 and scr5 configuration register these two registers contain the dc offset bytes. they can be used one by one. activation is controlled by the eno bit (scr0-2). with cal (xtr1...) levelmeter result can be read from scr 4/5 scr4 reset value: 00 h scr5 reset value: 00 h bit 7 6 5 4 3 2 1 0 low byte of dc-offset compensation note: = not implemented in muslic-s bit 7 6 5 4 3 2 1 0 high byte of dc-offset compensation note: = not implemented in muslic-s
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 78 2000.07.06 preliminary scr6a configuration register 6 configuration register scr6a, sets the receiving time slot and the receiving pcm- highway. in case of 16 bit linear mode time slot and pcm-highway for the most significant byte is selected. bit76543210 r-way rs6 rs5 rs4 rs3 rs2 rs1 rs0 reset value: 00 h r-way selects the pcm-highway for the receiving of pcm-data r-way = 0: pcm-highway a is selected r-way = 1: pcm-highway b is selected rs[6:0] selects the time slot (0 to 127) used for receiving the pcm-data the time slot-number is binary coded. 0 0 0 0 0 0 0: time slot 0 is selected 0 0 0 0 0 0 1: time slot 1 is selected .... .... 1 1 1 1 1 1 0: time slot 126 is selected 1 1 1 1 1 1 1: time slot 127 is selected
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 79 2000.07.06 preliminary scr6b configuration register 6 configuration register scr6b, sets the receiving time slot and the receiving pcm- highway in case of 16 bit linear mode for the least significant byte. bit76543210 r-way rs6 rs5 rs4 rs3 rs2 rs1 rs0 reset value: 00 h r-way selects the pcm-highway for receiving of linear data r-way = 0: pcm-highway a is selected r-way = 1: pcm-highway b is selected rs[6:0] selects the time slot (0 to 127) used for receiving linear data the time slot-number is binary coded. 0 0 0 0 0 0 0: time slot 0 is selected 0 0 0 0 0 0 1: time slot 1 is selected .... .... 1 1 1 1 1 1 0: time slot 126 is selected 1 1 1 1 1 1 1: time slot 127 is selected
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 80 2000.07.06 preliminary scr7a configuration register 7 configuration register scr7a, sets the transmit time slot and the transmit pcm- highway. in case of 16 bit linear mode time slot and pcm-highway for the most significant byte is selected. note: while programing the transmit time slot assignment, the pcm-highway needs to be switched off for the respective channel (pcmon=1, bit 3 of scr3). bit 7 6 5 4 3 2 1 0 x-way xs6 xs5 xs4 xs3 xs2 xs1 xs0 reset value: 00 h x-way selects the pcm-highway for transmitting pcm-data x-way = 0: pcm-highway a is selected x-way = 1: pcm-highway b is selected xs[6:0] selects the time slot (0 to 127) used for transmitting the pcm-data the time slot-number is binary coded. 0 0 0 0 0 0 0: time slot 0 is selected 0 0 0 0 0 0 1: time slot 1 is selected .... .... 1 1 1 1 1 1 0: time slot 126 is selected 1 1 1 1 1 1 1: time slot 127 is selected
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 81 2000.07.06 preliminary scr7b configuration register 7 configuration register scr7b, sets the transmit time slot and the transmit pcm-highway in case of 16 bit linear mode for the least significant byte. bit 7 6 5 4 3 2 1 0 x-way xs6 xs5 xs4 xs3 xs2 xs1 xs0 reset value: 00 h x-way selects the pcm-highway for transmitting linear data x-way = 0: pcm-highway a is selected x-way = 1: pcm-highway b is selected xs[6:0] selects the time slot (0 to 127) used for transmitting linear data the time slot-number is binary coded. 0 0 0 0 0 0 0: time slot 0 is selected 0 0 0 0 0 0 1: time slot 1 is selected .... .... 1 1 1 1 1 1 0: time slot 126 is selected 1 1 1 1 1 1 1: time slot 127 is selected
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 82 2000.07.06 preliminary scr8 configuration register 8 configuration register scr8 supplies the most important and time critical informations from the muslic. this register is read only. bit76543210 qio2 qio1 qi1 hook gnk slcx 0 0 reset value: 00 h slcx interrupt bit: summary output of the whole signalling register (tcr0). slcx = 0 no unmasked bit in the signalling register has toggled. slcx = 1 any unmasked bit in the signalling register has toggled. gnk indication if a ground connection is detected (filtered via the dupgnk- counter). the function is disabled in power down state (gnk is set to 0). gnk = 0 no ground connection was detected. gnk = 1 ground connection was detected. hook indication of the loop condition (filtered via the dup-counter or 2 x dup-counter in power down state). hook = 0 subscriber is on-hook. hook = 1 subscriber is off-hook. qi1 logical state of the input pin i1 of the qap. qi1 = 0 the corresponding pin at the digital interface of the qap is receiving a logic 0. qi1 = 1 the corresponding pin at the digital interface of the qap is receiving a logic 1. qio1 logical state of the programmable input/output pin io1 of the qap - even if not programmed as an input pin. 1) 1) if the input/output pin is programmed as an output the corresponding bit in the scr8 register is "1". qio1 = 0 the corresponding pin at the digital interface of the qap is receiving a logic 0. qio1 = 1 the corresponding pin at the digital interface of the qap is receiving a logic 1. qio2 logical state of the programmable input/output pin io2 of the qap - even if not programmed as an input pin. 1) qio2 = 0 the corresponding pin at the digital interface of the qap is receiving a logic 0. qio2 = 1 the corresponding pin at the digital interface of the qap is receiving a logic 1.
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 83 2000.07.06 preliminary the dup- (dupgndk-) counters filter the status-information and the input i1. the counters count down and generate enable signals for the registers if they are zero. then they start counting again at the programmed value. if a status information or the input signal changes the proper counter is set and continues counting down. there is one dup counter for vb/2, icon, lsup (generating slcx), the input pin i1 and for hook. for filtering the gnk information there is the dupgnk counter. in case of a mode change: 1. the actual status of hook is fixed and the actual hook counter is set 2. the dup- and dupgnk-counters are load with the double of the programmed value to avoid any influence of transients 3. in power down mode the counters are always load with the double of the programmed value scr9 configuration register 9 interrupt mask register bit7654321 0 qio2m qio1m qi1m hookm gnkm 1 1 1 reset value: ff h qio2m qio2m = 0 each change leads to an interrupt qio2m = 1 changes are neglected qio1m qio1m = 0 each change leads to an interrupt qio1m = 1 changes are neglected qi1m qi1m = 0 each change leads to an interrupt qi1m = 1 changes are neglected hookm hookm = 0 each change leads to an interrupt hookm = 1 changes are neglected gnkm gnkm = 0 each change leads to an interrupt gnkm = 1 changes are neglected
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 84 2000.07.06 preliminary scr10 configuration register 10 configuration register scr10 covers selection of operating modes for the muslic and sets the values for output pins of the qap. bit76543210 qio2 qio1 qo1 m2 m1 m0 0 0 reset value: 00 h m0, m1, m2 these bits define the mode selection for the muslic; see table below for details see chapter 5 ) note: in external ringing mode (rexten, xr2-7 = 1) when ring burst on (rbo) is detected, the output pin io1 of the qap is low active to drive directly the ring relay. qo1 value for the fixed output pin o1 of the qap. qo1 = 0 the corresponding pin at the digital interface of the qap is set to a logic 0. qo1 = 1 the corresponding pin at the digital interface of the qap is set to a logic 1. note: the output pin o1 of the qap is tristate after reset and will be enabled by the first sop command. qio1 value for the programmable input/output pin io1 of the qap if programmed as an output pin. if the bit rexten (xr2-7) is set to 1 (external ringing) the internally created ring burst on signal (for an external relay driver) is fed to qio1 ( chapter 5.5 ) qio1 = 0 the corresponding pin at the digital interface of the qap is set to a logic 0. m2 m1 m0 description 0 1 0 1 0 1 power-down high impedance (loop open, pdn power-down resistive (loop open, pdnr) 0 1 1 1 1 0 0 0 0 active state active state with meterpulses ground start 0 1 0 0 1 1 ringing state (ring pause) ringing state (ring burst on)
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 85 2000.07.06 preliminary stcr0 test configuration register 0 the test configuration register stcr0 is used for fuse operation and test only. reset value: 00 h stcr1 test configuration register 1 the test configuration register stcr1 is used for reserved operations of the peb 3465 (qap). reset value: 00 h qio1 = 1 the corresponding pin at the digital interface of the qap is set to a logic 1. qio2 value for the programmable input/output pin io2 of the qap if programmed as an output pin. qio2 = 0 the corresponding pin at the digital interface of the qap is set to a logic 0. qio2 = 1 the corresponding pin at the digital interface of the qap is set to a logic 1. bit76543210 fuse3 fuse2 fuse1 fuse0 0 0 0 0 fuse0 to fuse3 information for fuse operation bit76543210 rsv5 rsv4 rsv3 rsv2 rsv1 rsv0 0 0 rsv0 out of band ac-dac rsv0 = 0 rsv0 = 1 corner frequency of ac-dac = 31 khz corner frequency of ac-dac = 15 khz note: this bit come only into effect if bit enrsv (xtr8, bit0) is set to 1 rsv1 to rsv5 from peb 31666 to peb 3465
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 86 2000.07.06 preliminary 4.1.2 xop command to modify or evaluate test configurations, to select special functions, to control the coefficient rams, to get information for fusing and ecic and other common functions up to 15 bytes maybe transferred to or from the muslic, using the xop command (extended operation command). bit76543210 0 rw 1 0 lsel3 lsel2 lsel1 lsel0 rw read/write information: enables reading from the muslic or writing information to the muslic rw = 0 write to the muslic rw = 1 read from the muslic lsel length select information. this field identifies the subsequent data byte(s). lsel3 lsel 2 lsel 1 lsel 0 0000xr0 0001xr1 0010xr2 0011 xr3-xr6: ac-ram + dc-ram checksum 0100xr3-xr4: ac-ram checksum 0101 xr5-xr6: dc-ram che cksum 0110xr7: ecic1 (0 to 14) 0111xr8: ecic2 (15 to 29) 1110xr9 1000 xtr0 1001xtr1 and xtr2 1010 xtr0 to xtr8 1011fuse register 0 to fuse register 2 1100blocktest 1 to blocktest 3 1101 xtr15 to xtr18 1111reserved
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 87 2000.07.06 preliminary xr0 extended operation register 0 extended operation register 0 defines the four io-pins of the muppc. reset value: 00 h if the bit rexten (xr2-7) is set to 1 (unbalanced ringing) the io1 pin of the mupp c is switched to the ring pulse control function. thus a zero-crossing signal connected to the io1 (combined with the ringing mode, burst on/off) generates a correct switching signal for the ringer relay sent on i/o1-a...d (qap) of the selected subscriber line (see page 82 , page 84 and chapter 5.5 ). if the bit ex-mclk (xr2-2) and tst1 pin (no.32) are set to 1 and the io2 pin is set as an input the mupp ? is ready for external clocking (32.768 mhz) (the internal pll is shut down). if the tst1 pin (no.32) and the bit ex-mclk (xr2-2) is set to 1 and the io2 pin is set as an output the 32.768 mhz clock (output of the internal pll) is fed to the io2 pin. bit76543 2 1 0 mio4d mio3d mio2d mio1d mio4 mio3 mio2 mio1 mioid direction for programmable io - pins of the mupp ? io1 to io4 mioid = 0 sets the pin ioi as an input mioid = 1 sets the pin ioi as an output mioi value of programmable io - pins of the mupp ? io1 to io4 mioi = 0 sets the pin ioi to low or if it is read it is low mioi = 1 sets the pin ioi to high or if it is read it is high
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 88 2000.07.06 preliminary xr1 extended operation register 1 extended operation register 1 defines the data upstream persistency counters. reset value: 49 h bit76543210 dupgnk dup dupgnk to restrict the rate of upstream scr8-bit changes, deglitching (persistence checking) of the status information from the muslic may be applied. new status information will be transmitted upstream, after it has been stable for n milliseconds. n is binary programmable in the range of 4 to 64 ms in steps of 4 ms, with dupgnk = 0 h the deglitching time is 4ms. reset value is 20 ms. the gnk bit is influenced. (detailed info see scr8, page 82 and figure 29 .) dup to restrict the rate of upstream scr8-bit changes, deglitching (persistence checking) of the status information from the muslic may be applied. new status information will be transmitted upstream, after it has been stable for n milliseconds. n is binary programmable in the range of 1 to 16 ms in steps of 1 ms; with dup = 0 h the deglitching time is 1ms. reset value is 10 ms. the hook, slcx and the qi1-bits are influenced (different counters but same programming). (detailed info see scr8, page 82 and figure 29 .)
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 89 2000.07.06 preliminary xr2 extended operation register 2 extended operation register 2 defines basic operations for all channels. reset value: 14 h bit76543 2 1 0 rexten crsh_a crsh_b fixc idr ex-mclk fix-chan 0 rexten external ringing mode enabled (see chapter 5.5 ) rexten = 0 use internal ringing mode rexten = 1 use external ringing mode 1) crsh_a crash 2) on pcm-highway a (line dxa) crsh_a = 0 no crash detected crsh_a = 1 crash detected (bad programming in scr7a/b-registers) crsh_b crash on pcm-highway b (line dxb) crsh_b = 0 no crash detected crsh_b = 1 crash detected (bad programming in scr7a/b-registers) fixc the muslic uses either fixed coefficients or the programmed ones. fixc = 0 programmed coefficients used fixc = 1 fixed coefficients used idr initializes data ram idr = 0 normal operation is selected idr = 1 content of data ram is set to 0 (for test purposes) ex-mclk possibility to provide the muslic with an external clock (see xr0) ex-mclk = 0 normal operation is selected ex-mclk = 1 if the tst1 pin (no. 32) is set to 1 the internal pll is shut down or internal clock is connected to the pin mio2, respectively (see xr0) fix-chan selection between set programming and channel specific cram coefficients (only for ac- and tg-coefficients) fix-chan = 0 programming and mapping for the ac/tg-cram coefficients will be done in the normal way (cop command, channel mapping by car registers)
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 90 2000.07.06 preliminary the bit fix-chan switches between set programming and channel specific programming for the ac and tg coefficients. in the channel specific programming mode each channel has its own ac and tg coefficients. if fix-chan is set to 1, programming of the ac and tg cram coefficients can be done for 16 channels individually, but the mapping to the channels will be done in a fixed order. the dc coefficients will not be affected. xr3 to xr6 extended operation registers 3 to 6 xr3 to xr6 are the checksums of all the coefficient bytes written into the coefficient ram (cram) of the mupp ? by the cop-command. reading these bytes starts the sum generation. there are two identical blocks of crams (channels 0 to 7 and 8 to 15). each reading alternates the block access. fix-chan = 1 each channel can be programmed with his own ac/tg- cram coefficients. cop command will be handled as a sop command (channel specific). car0, car1 has to be programmed as usual. the mapping for the dc coefficients will be used as programmed but the mapping for the ac/ tg cram coefficients will be set to a fixed order. 1) with muslic-s this bit has to be set to 1 since internal ringing is not supported 2) a crash occurs, if 2 or more channels are programed to transmit (talk) in the same time slot on the same highway. in this case the crash-bit will be set, and transmission will be disabled for all affected channels.
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 91 2000.07.06 preliminary xr3 xr4 xr5 xr6 (algorithm of defining the checksum: x 16 + x 10 + x 7 + x + 1) (with that algorithm you can reach a fault coverage of: 1-2 ? 16 ) bit 7 6 5 4 3 2 1 0 low byte of ac-cram-checksum bit 7 6 5 4 3 2 1 0 high byte of ac-cram-checksum bit 7 6 5 4 3 2 1 0 low byte of dc-cram-checksum bit 7 6 5 4 3 2 1 0 high byte of dc-cram-checksum
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 92 2000.07.06 preliminary sum generation is done in the following manner. ac-cram-checksum the sequence of the coefficients is: tg1 set7 tg2 tg1 set6 tg2 ... ... tg1 set0 tg2 tgcsf im1 im2 im3 th1 th2 th3 set7 frx frr tstac ax ar accsf im1 ... set6 accsf ... ... im1 ... set0 accsf
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 93 2000.07.06 preliminary dc-ram-checksum the sequence of the coefficients is: using the ? checksum fill ? bytes (tgcsf, accsf, dccsf) it is possible to create a fixed set-checksum independent of changed coefficients. tsttx lpf hookl ramp tstdc set3 ttx agc dc ring dccsf tsttx ... set2 dccsf tsttx ... set1 dccsf tsttx ... set0 dccsf
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 94 2000.07.06 preliminary checksum to calculate the cram checksum the following shift register is implemented. figure 28 checksum algorithm: unsigned int checksum, newbyte; for (i=1;i= 0x8000) // if msb = 1 -> evaluate checksum with polynom checksum = (((checksum<<1)^newbyte)&0xffff)^0x0483; else checksum = (((checksum<<1)^ newbyte)&0xffff); } the fillbytes can be used to get a predefined checksum. the following example is given to get the checksum 0x0000 after every set. this is very useful since the sets can be changed without interfering and changing the complete checksum over all sets. 1. calculate the checksum until 1 byte before the 8 fillbytes (note: in order to calculate the fill bytes you should take into account that there is a need to have 9 bytes available in order to set a calculated checksum back to 0x0000. the ninth respectively the first byte is located within the cram at the following positions: ac-fill bytes: within ar-filter-coefficients nibble 14/15. dc-fill bytes: within dc-test-coefficients (tstdc) nibble 14/15. tg-fill bytes: within tg2/set0 nibble 14/15. 0 1 2 123 0 10 11 12 13 14 15 3 4 6 467 7 8 9 5 5 newbyte checksum peb31666_0001_checksum.emf
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 95 2000.07.06 preliminary 2. the next steps are to feed in 9 bytes that ? zero out ? after the xor feedbacks the result of the checksum algorithm: for (i = 1;i < 10;i++){ // take fillbyte out of checksum: fillbyte = (checksum<<1) & 0xff; // if msb = 1 checksum is evaluated with polynom if ((checksum & 0x8000) == 0x8000) fillbyte = fillbyte ^ 0x83; // if msb = 0 checksum no feedback if ((checksum & 0x1000) == 0x1000) fillbyte = fillbyte ^ 0x80; // calculate new checksum with fillbyte if (checksum >= 0x8000) checksum = (((checksum<<1)^ fillbyte)&0xffff)^0x0483; else checksum = (((checksum<<1)^ fillbyte)&0xffff); }
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 96 2000.07.06 preliminary xr7 and xr8 extended operation register 7 to 8 each of these two registers feasibles to read 15 bytes of design/status information generated by an external asic. xr7 xr8 xr7 and xr8 shows the data stream of the input pin id0. if the input pins id1, id2 and id3 = 1, id0 works as a serial input controlled by efsc and mclk. note: valid data is available two efsc-periods after execution of the ecic-read command (xop command). bit 7 6 5 4 3 2 1 0 ecic1 (byte 0 to byte 14) bit 7 6 5 4 3 2 1 0 ecic2 (byte 15 to byte 29)
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 97 2000.07.06 preliminary xr9 extended register 9 this register configures the operation of the pcm-interface reset value: 00 h bit7 6543210 c-mode c-s r-s drv_0 shift pcm-offset c-mode defines the clk-mode for the pcm-interface c-mode = 0: single clocking is used c-mode = 1: double clocking is used c-s transmit slope x-s = 0: transmission starts with rising edge x-s = 1: transmission starts with falling edge r-s receive slope r-s= 0: data is sampled with falling edge of pclk r-s= 1: data is sampled with rising edge of pclk drv_0 driving mode for bit 0 (only available with single clocking mode) drv_0 = 0: bit 0 is driven the whole pclk-period drv_0 = 1: bit 0 is driven during the first half of the pclk- period only shift shifts the access to dxa/b and dra/b for one pclk-period (only available with double clocking mode) shift = 0: no shift takes place shift = 1: access to dxa/b and dra/b is shifted for one pclk-per. pcm-offset offset in number of data-clock periods added to time slot 0 0 0: no offset is added 0 0 1: one data clock period is added ... 1 1 1 seven data clock periods are added
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 98 2000.07.06 preliminary xtr0 extended operation test register 0 1) extended operation test register xtr0 defines testing features. reset value: 00 h 1) the xtr-registers are not available with the muslic-s bit76543210 hit hir elm softon opim8m dlp03 dlp5 dispofi hit for ahv-slic test functions hit = 0 normal operation hit = 1 changes ahv-slic-interface (c1,c2) which set the tip wire to high impedance hir for ahv-slic test functions hir = 0 normal operation hir= 1 changes ahv-slic-interface (c1,c2) which set the ring wire to high impedance elm enable level meter elm = 0 normal operation, if lm2pcm = 1 the input to the levelmeter is switched to pcm voice-channel elm = 1 level meter function is enabled, if lm2pcm = 1 the output of the levelmeter is switched to pcm voice-channel softon sw-fuses are activated in the peb 3465 softon = 0 hw-fuses are activated softon = 1 sw-fuses are activated opim8m open fast digital impedance matching loop (im8m) opim8m = 0 normal operation opim8m = 1 opens fast digital im-loop (h im8m = 0) dlp03 disable lp03-lowpass dlp03 = 0 normal operation dlp03 = 1 disables programmable lowpass (h lp03 = 1) dlp5 disable lp5-lowpass dlp5 = 0 normal operation dlp5 = 1 disables programmable lowpass (h lp5 = 1) dispofi disable postfilter (dc path) dispofi = 0 normal operation dispofi = 1 disables postfilter
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 99 2000.07.06 preliminary xtr1 extended operation test register 1 xtr1 controls the level meter functions reset value: 00 h bit7 6 5 4 3210 cal lmsel1 lmsel0 lmnotch lmbp lm2pcm pcm2dc itime cal enable levelmeter result register cal = 0 normal operation (offset register - scr4/scr5 - is read) cal = 1 levelmeter result register is read lmsel selects levelmeter and thresholdpairs lmnotch bandpass or notchfilter function for levelmetering ac lmnotch = 0 bandpass function lmnotch = 1 notchfilter function lmbp activates the bandpass or notchfilter in the ac transmit path lmbp = 0 normal operation lmbp = 1 bandpass/notchfilter enabled lm2pcm switches the selected levelmeter signal to the pcm voice-channel lm2pcm = 0 normal operation lm2pcm = 1 switches the selected levelmetersignal to the pcm voice-channel pcm2dc switches the receive pcm voice-channel to dc-output pcm2dc = 0 normal operation pcm2dc = 1 switches the receive pcm voice-channel to dc-output itime integration time of ac and ttx levelmeter itime = 0 16 ms integration time itime = 1 256 ms integration time lmsel1 lmsel0 0 0 dc-levelmeter thresholdpair 0 0 1 dc-levelmeter thresholdpair 1 1 0 ac-levelmeter 1 1 ttx-levelmeter
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 100 2000.07.06 preliminary xtr2 extended operation test register 2 extended operation test register xtr2 defines testing features (see chapter 7 ). reset value: 00 h bit76543210 ring-on ddcc dcad16 eramp erect ac- adcpd ac- dacpd afe-off ring-on interrupt dc-characteristic and enables the ringing offset ring-on = 0 normal operation ring-on = 1 opens dc-loop (hdcc = 0) and enables the ringing offset ddcc disable dc-characteristic ddcc = 0 normal operation ddcc = 1 bridges dc-loop (h dcc = 1) dcad16 dc gain of 16 in ad direction dcad16 = 0 normal operation dcad16 = 1 gain of 16 eramp enable ramping generator eramp = 0 ramping generator off eramp = 1 ramping generator on erect enable rectifier in dc-levelmeter erect = 0 normal operation (hrect = 1) erect = 1 enables rectifier ac-adcpd adc is set to power down (transmit path is opened) ac-adcpd = 0 normal operation ac-adcpd = 1 transmit path is inactive ac-dacpd dac is set to power down (receive path is opened) ac-dacpd = 0 normal operation ac-dacpd = 1 receive path is inactive afe-off analog front end is activated or deactivated afe-off = 0 normal operation afe-off = 1 the analog front end is deactivated
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 101 2000.07.06 preliminary xtr3 extended operation test register 3 extended operation test register xtr3 defines the basic muslic settings which enable / disable the programmable digital filters. reset value: 00 h bit76543210 dhp-x dhp-r th frx frr ax ar im dhp-x disable transmit highpass for test reasons dhp-x = 0 transmit highpass filter is enabled dhp-x = 1 transmit highpass filter is disabled dhp-r disable receive highpass for test reasons dhp-r = 0 receive highpass filter is enabled dhp-r = 1 receive highpass filter is disabled th 1) set transhybrid balancing filter - together with the bit fixc (xr2,bit 4). for fixc = 1: the th-filter is set to h th = for z brd ; for fixc = 0: th = 0 th-filter is disabled th = 1 th-filter is enabled (use programmed values) frx 1) enable frx-(frequency response transmit) filter for fixc = 0: frx = 0 frx-filter is disabled (h frx = 1) frx = 1 frx-filter is enabled (use programmed values) frr 1) enable frr-(frequency response receive) filter for fixc = 0: frr = 0 frr-filter is disabled (h frr = 1) frr = 1 frr-filter is enabled (use programmed values) ax 1) set ax- (amplification/attenuation transmit) filter for fixc = 0: ax = 0 ax-filter is set to default value (h ax = 10 db) ax = 1 ax-filter is enabled (use programmed values) ar 1) set ar- (amplification/attenuation receive) filter for fixc = 0: ar = 0 ar-filter is set to default value (h ar = ? 15.11 db) ar = 1 ar-filter is enabled (use programmed values)
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 102 2000.07.06 preliminary xtr4 extended operation test register 4 extended operation test register xtr4 defines testing features. reset value: 00 h im 1) activates or deactivates the 64 khz filter im = 0 64 khz filter is deactivated (h im = 0) im = 1 64 khz filter is activated 1) for muslic-s these filters are always enabled; depending on bit fixc (xr2, bit 4) the default settings or the programmed coefficients are used. bit76543210 dlb-8m dlb-64k dlb-32k dlb- pcm alb-8m 0 0 dchold dlb-8m ac digital loop: 8 mhz in/output is short cut dlb-8m = 0 normal operation dlb-8m = 1 8 mhz in/output is short cut dlb-64k ac digital loop: 64 khz in/output is short cut dlb-64k = 0 normal operation dlb-64k = 1 64 khz in/output is short cut dlb-32k ac digital loop: 32 khz in/output is short cut dlb-32k = 0 normal operation dlb-32k = 1 32 khz in/output is short cut dlb-pcm ac digital loop: pcm in/output is short cut dlb-pcm = 0 normal operation dlb-pcm = 1 pcm in/output is short cut alb-8m ac analog loop: 8 mhz in/output is short cut alb-8m = 0 normal operation alb-8m = 1 8 mhz short cut dchold holds the current dc-output dchold = 0 normal operation dchold = 1 dc-output is held
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 103 2000.07.06 preliminary xtr5 extended operation test register 5 xtr5 defines testing functions reset value: 00 h bit76543210 dc-dlb dc- albit 0dc- albil dc-albv dclmu2 dclmu1 dclmu0 dc-dlb dc digital loop: 1 mhz in/output is short cut dc-dlb = 0 normal operation dc-dlb = 1 1 mhz in/output is short cut dc-albit dc analog loop: it is switched to dcp/dcn dc_albit = 0 normal operation dc_albit = 1 it is switched to dcp/dcn dc-albil dc analog loop: il is switched to dcp/dcn dc_albil = 0 normal operation dc_albil = 1 il is switched to dcp/dcn dc-albv dc analog loop: va, vb, vbim, vddim is switched to dcp/dcn dc_albv = 0 normal operation dc_albv = 1 va, vb, vbim, vddim is switched to dcp/dcn dclmu selects the signal switched to the dc-levelmeter dclmu2 dclmu1 dclmu0 0 00it 0 10il 1 00va 1 01vb 1 10vbim 1 11vddim
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 104 2000.07.06 preliminary xtr6 extended operation test register 6 xtr6 defines testing functions reset value: 00 h bit76543210 ttxl gainbb noagc ilitmux cot16 ditoff axg0 arg0 ttxl enables current measurement for ttx ttxl = 0 normal operation ttxl = 1, im = 0 and opim8m = 1 enables ttx current measurement gainbb this bit enables an additional dc-gain of about 4 db (factor of 1.6) inside the qap in receive direction. especially for test purposes in hir/hit mode it enables the use of the full voltage range of the ahv-slic. gainbb = 0 normal operation gainbb = 1 additional dc-gain is set noagc disable automatic gain control for ttx noagc = 0 normal operation noagc = 1 disable automatic gain control ilitmux il changes to it and vice versa ilitmux = 0 normal operation ilitmux = 1 il changes to it and vice versa cot16 cut off transmit path cot16 = 0 normal operation cot16 = 1 cut off transmit path ditoff disables the dither for noiseshapers. obsolete for qap v1.2 or higher. ditoff = 0 normal operation ditoff = 1 dither disabled axg0 0 db gain for transmit path axg0 = 0 normal operation axg0 = 1 0 db gain for transmit path arg0 0 db gain for receive path arg0 = 0 normal operation arg0 = 1 0 db gain for receive path
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 105 2000.07.06 preliminary table 10 important factors for the calculation of voltages and slopes in different modes by using muslicos for all values: "active" selected in scr10 and scr0.ente=1 factor with peb31666 v1.3 and xtr6.gainbb=0 or peb 31666 v1.2 factor with peb31666 v1.3 and xtr6.gainbb=1 scr0.n/bb=0 0.625 1 scr0.n/bb=1 1 1 hir (high impedance ring) or hit (high impedance tip) and scr0.n/bb=1 0.3125 0.5 hir (high impedance ring) or hit (high impedance tip) and scr0.n/bb=0 behaves like scr0.n/bb=1 0.3125 0.5
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 106 2000.07.06 preliminary xtr7 extended operation test register 7 xtr7 informs how many peb 3465 are connected to the peb 31666 and controls the level meter functions reset value: 00 h note: this information is available after the first afsc-pulse bit 7 6 5 4 3 2 1 0 qdetq4 qdetq3 qdetq2 qdetq1 0 0 calmux1 calmux0 qdetqi informs about peb 3465 connection qdetqi = 0 there is no peb 3465 connected to the i-th interface qdetqi = 1 there is a peb 3465 connected to the i-th interface calmux selects levelmeter source read by scr4/scr5 if cal = 1 (bit 7 of xtr1) calmux1 calmux0 0 0 dc-levelmeter thresholdpair 0 0 1 dc-levelmeter thresholdpair 1 1 0 ac-levelmeter 1 1 ttx-levelmeter
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 107 2000.07.06 preliminary xtr8 extended operation test register 8 xtr8 enables reserved registers reset value: 00 h xtr9 to xtr11 extended operation test register 9 to 11 (for internal use only) these bytes are used for the fuse operation of the peb 3465. xtr9 reset value: 00 h xtr10 reset value: 00 h xtr11 reset value: 00 h bit76543210 0000000enrsv enrsv enables reserved registers (stcr1, xtr15 to xtr18) enrsv = 0 normal operation enrsv = 1 reserved registers are enabled note: in contrast to the other xtr-registers it is possible to use bit enrsv without setting bit ente (scr0, bit1) to 1. bit76543210 0fuse 0 qap 1 fuse 0 qap 2 fuse 0 qap 3 fuse 0 qap 4 bit76543210 fuse 1 qap 1 fuse 1 qap 2 fuse 1 qap 3 fuse 1 qap 4 fuse 2 qap 1 fuse 2 qap 2 fuse 2 qap 3 fuse 2 qap 4 bit76543210 fuse 3 qap 1 fuse 3 qap 2 fuse 3 qap 3 fuse 3 qap 4 fuse 4 qap 1 fuse 4 qap 2 fuse 4 qap 3 fuse 4 qap 4
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 108 2000.07.06 preliminary xtr12 to xtr14 extended operation test register 12 to 14 (for internal use only) xtr12 to xtr14 are reserved for the internal blocktest function. reset value: 00 h note: in order to allow operation of the internal block tests, the test pin of the mupp peb 31666 (pin 32) must be connected to high input voltage. xtr15 to xtr17 extended operation test register 15 to 17 xtr15 to xtr17 are reserved for transfer of information from the peb 31666 to the peb 3465. reset value: 00 h xtr18 extended operation test register 18 xtr18 is reserved for future use. reset value (always returned in current version): 00 h
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 109 2000.07.06 preliminary 4.1.3 top command with the top command the tcr0 and tcr1 registers can be read. each channel has its own registers addressed by the time slot or by address bit76543210 0r1100lsel1lsel0 r read information: enables reading from the muslic r = 0 no operation r = 1 read from muslic lsel length select information this field identifies the selected tcr register(s) and the handling of interrupts too. lsel 1 lsel 0 0 0 tcr0 (reset of the interrupt) 0 1 tcr1 (not masked interrupts are not affected) 1 1 tcr0 and tcr1 (reset of the interrupt)
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 110 2000.07.06 preliminary tcr0 configuration register 0 tcr0 is the signalling register. it indicates status information of each channel. if there is any change of one or more bits it is indicated via the sclx bit in the scr8-channel. each bit, except the res bit, can be masked by the scr2 register (see also figure 29 ). reset value: 02 h bit76543 2 1 0 vb/2 icon temp fail mva lsup res 0 note: = not defined with muslic-s vb/2 programable threshold for detecting the ahv-slic-feeding-voltage interrupt masked in power denial and ringing state vb/2 = 0 line voltage smaller than threshold vb/2 = 1 line voltage larger than threshold icon current limitation information, interrupt masked in power denial and ringing state icon = 0 resistive feeding icon = 1 constant current feeding temp temperature alarm of the ahv-slic which is signalled through the ahv-slic interface (see chapter 3.4 ) temp = 0 normal temperature temp = 1 temperature alarm from ahv-slic detected fail mclk or fsc fail: not the right count of clock cycles between two frame syncs fail = 0 no clock fails are detected fail = 1 clock fails are detected the fail bit is not influenced by the dup-counter (each failure is reported). mva internal measurement results shown in the tcr1-0 and tcr1-1 are valid or not valid (see chapter 7 ) mva = 0 the level metering results are not valid mva = 1 the level metering results are valid lsup line supervision (of broken line) lsup = 0 the transversal current is lower than the programmed level lsup = 1 the transversal current is higher than the programmed level
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 111 2000.07.06 preliminary any change of these bits (except the fail bit: only the positive going is reported) is signalled via the interrupt-bit (slcx) in the scr8-register. there are two types of generating an interrupt: ? each toggling of a non-masked tcr0-bit combined with a dup-counter ? toggling of the non-masked temp or mva-bit and positive going fail bit (no filtering by the dup-counter) the status information is stored in the tcr0-register and an interrupt is generated but only if there isn ? t a not-handled interrupt. reading the tcr0-register gives the frozen interrupt status, clears the interrupt and enables the signalling of a further interrupt but not until after at least two 8 khz frames. note: the hook and the gnk signalling are directly filtered by their own dup(gnk)- counters and these results are directly put into the register scr8 (see page 82 ). tcr1 configuration register 1 tcr1 indicates interrupt information and level meter results of one channel. reset value: 00 h res reset status res = 0 no reset has occurred res = 1 reset has occurred via reset-pin or via power on reset bit76543 2 1 0 nmvb/2 nmicon nmtemp nmfail nmmva nmlsup rlm1 rlm0 note: = not defined with muslic-s nmvb/2 to nmlsup not masked signalling information. (the meaning of each bit is the same as described above.) reading this register won ? t affect any stored information. rlm1 and rlm0 result levelmetering rlm1 rlm0 0 0 below both levels x 1 above level 0 1 x above level 1
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 112 2000.07.06 preliminary figure 29 interrupt logic (block structure) 1) in power down and ringing mode changes of vb/2 and icon are masked. 2) tcr0 is locked if one of the signals changes and is enabled after reading. each change of tcr0 sets the interrupt bit slcx to 1. reading tcr0 sets slcx to 0 but not before two 8 khz frames. a take over of the signal fail from tcr1 to tcr0 cleares this signal in tcr1. 3) in power down mode the persistency counter 2 x dup is used. 4) realized in ground start mode. ezm07113.emf dup dup nmvb/2 nmicon nmtemp nmfail nmmva nmlsup rlm1 rml0 dup vb/2 icon temp fail mva lsup persistency counter tcr1 vb/2m iconm tempm failm mvam lsupm vb/2 icon temp fail mva lsup res slcx res not masked signalling register mask register signalling register dup dup dup gnk io2 io1 i1 hook / lsup gnk scr2 tcr0 2) 3) 1) 1) valid only in active mode 4) slck gnk hook qi1 qio1 qio2 scr8
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 113 2000.07.06 preliminary 4.1.4 cop command with a cop command coefficients for the programmable filters can be written to or read from the muslic. (filter optimizing to different applications is supported by the software package muslicos.) the coefficients are gathered to 8 and 4 sets respectively. so an optimum is reached between supplying each channel, handling and memory space. figure 30 gives an overview of the coefficient ram (cram) structure. to assign a set to a channel the copi command is used. in channel specific programming mode (fix-chan = 1 in xr2) the cop command will be handled as a channel specific sop command. bit76543 2 1 0 icram rw 0 0 0 1 wcram1 wcram0 bit76543 2 1 0 set2 set1 set0 code 4 code 3 code 2 code 1 code 0 icram initialize cram icram = 0 only one coefficient is programmed (destination is coded in the following byte) (no influence of wcram1 and wcram0) icram = 1 the whole ac- or dc-cram is written with the information of the following byte rw read/write rw = 0 subsequent data is written to the muslic rw = 1 read data from the muslic wcram1 and wcram0 write to cram (only valid in combination with icram=1) wcram1 wcram0 0 0 no write 0 1 ac-cram 1 0 dc-cram 1 1 ac-cram and dc-cram
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 114 2000.07.06 preliminary set includes the number of coefficient set set 0 to set 7 for the 8 sets of ac-coefficients and the 8 sets of tone generator 1 and 2 set 0 to set 3 for the 4 sets of dc-coefficients set2 set1 set0 000set 0 001set 1 010set 2 011set 3 100set 4 101set 5 110set 6 111set 7
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 115 2000.07.06 preliminary code includes the number of following bytes and filter-addresses 1) 1) for generating a correct checksum all not used bits must be set to 0. code4 code3 code2 code1 code0 0 0000th-filter coefficients (part 1)(followed by 8 bytes of data) 0 0001th-filter coefficients (part 2)(followed by 8 bytes of data) 0 0010th-filter coefficients (part 3)(followed by 8 bytes of data) 0 0011frx-filter coefficients (followed by 8 bytes of data) 0 0100frr-filter coefficients (followed by 8 bytes of data) 0 0101ax-filter coefficients (followed by 8 bytes of data) 0 0110ar-filter coefficients (followed by 8 bytes of data) 0 0111tg1-filter coefficients (followed by 8 bytes of data) 0 1000tg2-filter coefficients (followed by 8 bytes of data) 0 1001ac test coefficients (followed by 8 bytes of data) 0 1010im-filter coefficients (part 3)(followed by 8 bytes of data) 0 1011im-filter coefficients (part 1)(followed by 8 bytes of data) 0 1100im-filter coefficients (part 2)(followed by 8 bytes of data) 0 1101tg csf (checksum f ill) (followed by 8 bytes of data) 0 1110ac csf (checksum f ill) (followed by 8 bytes of data) 1 0000ttx test coefficients (followed by 8 bytes of data) 1 0001ttx coefficients (followed by 8 bytes of data) 1 0010agc coefficients (followed by 8 bytes of data) 1 0011lp-filter coefficients (followed by 8 bytes of data) 1 0100hook level coefficients (followed by 8 bytes of data) 1 0101dc test coefficients (followed by 8 bytes of data) 1 0110ringing coefficients (followed by 8 bytes of data) 1 0111dc-characteristic coefficients(followed by 8 bytes of data) 1 1000ramp generator, ringer delay coefficients (followed by 8 bytes of data) 1 1001dc csf (checksum fill) (followed by 8 bytes of data)
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 116 2000.07.06 preliminary figure 30 overview of coefficient sets (fix-chan = 0 in xr2) in case of channel specific programming mode (fix-chan = 1 in xr2) the ac- and tg- coefficients can be selected individually for all channels. in this mode 16 sets are available for ac, tg1 and tg2. ezm07114.emf dc set 3 tsttx lpf hookl ramp tstdc ttx agc dc ring dccsf tg1 set 7 tg1 ac set 7 im th frx frr tstac ax ar dc set 0 tsttx lpf hookl ramp tstdc ttx agc dc ring dccsf ac set 0 im th frx frr tstac ax ar tg1 set 0 tg1 tg2 set 7 tg2 tg2 set 0 tg2
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 117 2000.07.06 preliminary 4.1.5 copi command the copi command allows to assign the sets of the coefficient rams to a selected channel (given by the time slot or by address). in channel specific programming mode (fix-chan = 1 in xr2) the assignment of ac and tg coefficients is ignored. bit76543 2 1 0 b rw 0 0 1 0 lsel1 lsel0 b broadcast b = 0 only one channel (time slot) is programmed b = 1 all channels (up to 16) are programmed with the same information rw read/ write rw = 0 subsequent data is written to the muslic rw = 1 set assignment is read lsel length select information. this field identifies the subsequent data byte(s). lsel 1 lsel 0 00car0 01car1 1 1 car0 and car1
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 118 2000.07.06 preliminary car0 coefficient set assignment register 0 car0 indicates ac and dc coefficients set assignment. reset value: 00 h bit76543 2 1 0 dc1 dc0 ac2 ac1 ac0 0 0 hload dc ac hload hook for load hload = 0 normal operation hload = 1 load is activated (lp03 will be preset; for normal operation this bit should not be used) dc1 dc0 0 0 dc coefficient set 0 0 1 dc coefficient set 1 1 0 dc coefficient set 2 1 1 dc coefficient set 3 ac2 ac1 ac0 0 0 0 ac coefficient set 0 0 0 1 ac coefficient set 1 0 1 0 ac coefficient set 2 0 1 1 ac coefficient set 3 1 0 0 ac coefficient set 4 1 0 1 ac coefficient set 5 1 1 0 ac coefficient set 6 1 1 1 ac coefficient set 7
peb 3465, peb 31666/4, peb 4166/4 muslic programming the muslic preliminary data sheet 119 2000.07.06 preliminary car1 coefficient set assignment register 1 car1 indicates tone generator coefficients set assignment. reset value: 00 h tg1 tg2 bit76543 2 1 0 tg1.2 tg1.1 tg1.0 tg2.2 tg2.1 tg2.0 0 0 tg1.2 tg1.1 tg1.0 0 0 0 tone generator 1 set 0 0 0 1 tone generator 1 set 1 0 1 0 tone generator 1 set 2 0 1 1 tone generator 1 set 3 1 0 0 tone generator 1 set 4 1 0 1 tone generator 1 set 5 1 1 0 tone generator 1 set 6 1 1 1 tone generator 1 set 7 tg2.2 tg2.1 tg2.0 0 0 0 tone generator 2 set 0 0 0 1 tone generator 2 set 1 0 1 0 tone generator 2 set 2 0 1 1 tone generator 2 set 3 1 0 0 tone generator 2 set 4 1 0 1 tone generator 2 set 5 1 1 0 tone generator 2 set 6 1 1 1 tone generator 2 set 7
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 120 2000.07.06 preliminary 5 operating modes the muslic supports 4 different operating modes: power down (pdown), active, ringing and ground start which are controlled via the lower 3 bits of the configuration register scr10: m2 (scr10-4) m1 (scr10-3) m0 (scr10-2) description 0 1 0 1 0 1 power-down high impedance (pdnh) power-down resistive (pdnr) 0 1 1 1 0 0 active state active state with meterpulses 0 1 0 0 1 1 ringing state (ring pause) ringing state (ring burst on) 1 0 0 ground start 0 1 1 must not be used
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 121 2000.07.06 preliminary figure 31 operating modes rev. pol. meterpulse ring burst on ring pause power down (pdnh) ttx burst on active reset poweron- reset hw-reset 010 000 010 010 ttxno=1 111 001 m2, m1, m0 bits (e.g. 100 ) 110 001 101 power down (pdnr) ground start 100 101 110 ttxno=0 110 110 emf.07115.emf
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 122 2000.07.06 preliminary table 11 operating modes muslic-e muslic mode configuration register (mupp c) ahv-slic interface qap m2 scr10 bit 4 m1 scr10 bit 3 m0 scr10 bit 2 io2 1) scr10, bit6 n/bb scr0 bit 6 act2 scr1 bit 2 gainbb 2) xtr6 bit 6 hir 2 xtr0 bit 6 hit 2 xtr0 bit 7 load c1 c2 c3 1 boost- factor 3) power-down high impedance (pdnh) {+ 5k} 0 0 0 {io2} x xxxxxml {io2}0 power-down resistive (pdnr) 1 1 1 x x xxxxxl mx0 active state (act) {+ 5k} 010{io2}000000hm{io2}0 active state reduced battery (act2) {+ 5k} 010{io2}010000hl{io2}0 active state (load) {+ 5k} 0 1 0 {io2} 0 0 0 0 0 1 l l {io2} 0 active state red. batt (load) {+ 5k} 0 1 0 {io2} 0 1 0 0 0 1 l l {io2} 0 active boost state 50ma (bb-50) 01001xx00xmm01 active boost state 100ma (bb-100) 01011xx00xmm11 active state with meterpulses (act) 110{io2}000000hm{io2}0 active state with meterpulses red. batt. (act2)110{io2}010000hl{io2}0 active state, meterpulses (load) {+ 5k} 1 1 0 {io2} 0 0 0 0 0 1 l l {io2} 0 active state, meterpulses, red. batt. (load) {+ 5k} 1 1 0 {io2} 0 1 0 0 0 1 l l {io2} 0 active boost state with meterpulses 50ma (bb-50)11001xx00xmm01 active boost state with meterpulses 100ma (bb-100)11011xx00xmm11 high impedance ring (hir) {+ gainbb} {+ 5k} x 1 0 {io2} x x {gainbb} 1 0 x l h {io2} {gainbb} high impedance tip (hit) {+ gainbb} {+ 5k} x 1 0 {io2} x x {gainbb} 0 1 x m h {io2} {gainbb} high impedance ring/tip (hirt) {+ gainbb} {+ 5k} x 1 0 {io2} x x {gainbb} 1 1 x h h {io2} {gainbb} high impedance ring (hir) {+ gainbb} {+ 5k} x 0 1 {io2} x x {gainbb} 1 0 x l h {io2} {gainbb} high impedance tip (hit) {+ gainbb} {+ 5k} x 0 1 {io2} x x {gainbb} 0 1 x m h {io2} {gainbb} high impedance ring/tip (hirt) {+ gainbb} {+ 5k} x 0 1 {io2} x x {gainbb} 1 1 x h h {io2} {gainbb} high impedance ring (hir) {+ gainbb} {+ 5k} 1 0 0 {io2} x x {gainbb} 1 0 x l h {io2} {gainbb} high impedance tip (hit) {+ gainbb} {+ 5k} 1 0 0 {io2} x x {gainbb} 0 1 x m h {io2} {gainbb} high impedance ring/tip (hirt) {+ gainbb} {+ 5k} 1 0 0 {io2} x x {gainbb} 1 1 x h h {io2} {gainbb}
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 123 2000.07.06 preliminary ground start {+ gainbb} {+ 5k} 1 0 0 {io2} x x {gainbb} x x x m h {io2} {gainbb} ringing state (ring pause) 50ma 0010xxx00xmm01 ringing state (ring burst on) 50ma 1010xxx00xmm01 ringing state (ring pause) 100ma 0011xxx00xmm11 ringing state (ring burst on) 100ma 1011xxx00xmm11 must not be used 0 1 0 x 0 x 1 0 0 x h m x 1 must not be used 110x0x100xllx1 must not be used 0 1 1 x x x 0 x x x m l x 0 transient state - this state occurs for 2ms after a change from any powerdown mode (pdnh or pdnr) to an active mode (act, act2 ) 1) it is assumed that the resp. io2 pin of the qap is connected together with the resp. c3 pin of the ahv-slic 2) these bits are masked with bit ente (scr0, bit1); come only into effect if ente is set to 1 3) analog dc-gain in qap, see also table 10 . note: {io2} means that it can be either 0 or 1, but all {iom2} in one row are of the same logical state; if it is 1, the additio nal explanation in the first column is valid {+5k} {gainbb} means that it can be either 0 or 1, but all {gainbb} in one row are of the same logical state; if it is 1, the additio nal explanation in the first column is valid {+gainbb} table 11 operating modes muslic-e (continued) muslic mode configuration register (mupp c) ahv-slic interface qap m2 scr10 bit 4 m1 scr10 bit 3 m0 scr10 bit 2 io2 1) scr10, bit6 n/bb scr0 bit 6 act2 scr1 bit 2 gainbb 2) xtr6 bit 6 hir 2 xtr0 bit 6 hit 2 xtr0 bit 7 load c1 c2 c3 1 boost- factor 3)
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 124 2000.07.06 preliminary 5.1 reset behaviour the muslic has 2 different reset sources that are internally connected. the reset pin , which work asynchronously to the external clocks. power on reset if internal vdd rises above typ. 2.33 v the mupp ? is reset by power on reset. both sources set the muslic to the basic setting modes (see below). the pin reset of the mupp c and the qap has a schmitt-trigger input to reduce the sensitivity for spikes. in addition the pin reset has a spike rejection. all spikes smaller than 50 ns are neglected. the pin reset can be driven to 1 for an unlimited time but at least 2 s is recommended. in the mupp ? a reset activates the reset routine - but only if the mclk is present - which lasts at least two 2 khz periods for setting the default values. after this time and if an external reset is not active (reset = 0) the mupp c starts the normal (default) operation at the beginning of the next 8 khz frame (fsc). the pcm and the ?-interface are reset. running communication is stopped. in the qap a reset works asynchronously and no reset routine is necessary. the normal (default) operation of the qap starts at the beginning of a 2 khz frame (afsc) as soon as the external reset (reset = 0) is released.
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 125 2000.07.06 preliminary 5.2 basic setting modes after initiating a reset in the mupp c (by the reset pin or power on reset), the reset bit (tcr0 bit1 = res) is set to one and the slcx-interrupt (scr8) is activated. reading the tcr0 register clears the interrupt and the res-bit. after resetting the mupp ?, the muslic is switched automatically to its basic settings in which internal default values for all filters and parameters (ac and dc) are used. all subscriber lines are switched to high impedance state, no supervision can be done (muslic is set to power down high impedance state). the muslic can be programmed or configured via the c interface actions initialized by a reset: all configuration registers are set to their default values (note that the coefficient ram is not reset) ac- and dc-loop use the default values and not the programmed ones (see below) all bits of the signalling register tcr0 are masked and reset to 0 without the res-bit the scr8 bits are set to 0 except slcx, slcx is set to 1 (the io's are set to input pins) the res-bit (tcr0, bit1) is set to 1 to indicate that a reset has taken place intr is set to 1 (intel-mode) or 0 (motorola-mode) due to the power on reset bit (tcr0, bit 1) the ? interface is ready for receiving data outputs of pcm interface (tca, tcb, dxa, dxb) are switched to high impedance, afsc, adcl, add1, add2 to zero c1 and c2 represent pdnh mode boosted battery is reset to normal feeding reverse polarity is reset to normal polarity a-law is chosen table 12 default dc values (fixc ( xr2 bit 4) = 1) dc i lim 24 ma limit for constant current v lim 38 v voltage of limit between constant current and resistive char. v const 40 v constant voltage boostgain 1.3 additional gain in boosted battery mode r fs 375 ? feeding resistance (excluding the external fuse resistors) f ring 25 hz ring frequency a ring 62 vrms ring rms-value at ring/tip wire dc offset ring 22 v ring offset f ringlp 75 hz corner frequency of ring-lowpass
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 126 2000.07.06 preliminary off-hookpd 2 ma power-down current for off-hook detection off-hookact 8 ma off-hook detection in active with 2 ma hysteresis off-hookring 5 ma dc-current for off-hook detection in ringing mode linesup 5 ma current for line-supervision levelmeter1 8 ma first levelmeter threshold levelmeter2 12 ma second levelmeter threshold levelmeter3 21 ma third levelmeter threshold levelmeter4 25 ma fourth levelmeter threshold gkd1 17 ma first threshold-current for ground key detection gkd2 40 ma second threshold-current for ground key detection ringtip 52 v threshold at ring/tip wire dc-lowpass 0.3/20 hz dc-lowpass set to 0.3 and 20 hz respectively constramp 300 v/s slope of the ramp while testing delay ring 0 ms delay of ring burst srend1 1/128 soft-reversal threshold 1 (referred to the input of the ramp generator) srend2 1/512 soft-reversal threshold 2 (referred to the input of the ramp generator) srduration ca. 80 ms duration of a soft-reversal-sequence dup 10 ms data upstream persistency counter is set to 10 ms dupgnk 20 ms data upstream persistency counter for gnk is set to 20 ms table 12 default dc values (continued)(fixc ( xr2 bit 4) = 1) (continued)
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 127 2000.07.06 preliminary table 13 default ac values ac im-filter 900 ? approximately 900 ? real input impedance th-filter th brd approximately brd-impedance for balanced network ax 10 db attenuation transmit (this means about 0 db) ar ? 15.11 db attenuation receive (this means about ? 7 db) attx 4 vrms teletax generator amplitude at ring / tip wire at ahv- slic f ttx 16 khz teletax generator frequency; tg1 1008 hz tone generator 1 and ac -levelmeter bandpass ( ? 14 dbm0) tg2 2000 hz tone generator 2 (+ 2 db compared to tg1)
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 128 2000.07.06 preliminary 5.3 power down (pdown) and standby scr10: (m0/m1/m2=0/0/0,1/1/1) after a reset (including the power on reset) or programing the scr10-byte (scr10- 4 .. scr10, bit 4 ... bit 2) the muslic is set to power down state (in case of reset power-down high impedance). in power down all functions which are not necessary are disabled to minimize power consumption. this can be done for all the channels or only for the not active ones. while the interface is fully working - including programmability of the registers with sop or xop commands and the coefficient ram (cop commands) - the rest of the muslic is turned off. in case of power-down resistive supervision of the line remains active. therefore power-down resistive is the proper standby mode of muslic in on-hook state for most applications. the change of the line state is reported via the hook-bit in scr8. to avoid spurious off-hook indications caused by longitudinal induction the hook-bit is low pass filtered (programmable with the dup-counter). in power down mode the ahv-slic can be set into two different modes: 1. pdnr, the resistive mode which provides a connection of 5 k ? from tip and ring to bgnd and vbat, respectively. supervision of the line remains active. 2. pdnh, offers high impedance at tip and ring, no hook-detection or supervision is present
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 129 2000.07.06 preliminary 5.4 active mode (act) scr10: (m0/m1/m2=0/1/0,0/1/1) in active mode ( ? conversation state ? ) both ac-and dc-loop are fully working. the output voltage at the qap (dcp, dcn) is controlled via the it input pin in such a way, that it behaves like a constant current source which automatically turns into a programmable resistive feeding source due to the dc-characteristic values. the ternary ahv-slic interface is set to one of the active modes. polarity the muslic supports either normal or reverse polarity which is set by the polnr-bit (scr0, bit 7). a 180 phase shift of the dc-loop is done. the performance and the functionality is not be influenced by that. boosted battery to feed subscriber lines with enhanced loop resistance the muslic-e supports the boosted battery mode. the ahv-slic interface pins (c1, c2) are set to boosted battery (bb) mode and the maximum dc output voltage is extended to 140 v. meterpulses the muslic supports two different kinds of meterpulses: meterpulses with 12/16 khz (teletax metering) and with polarity reversal. the decision between these two types is made by the bit ttxno (scr1, bit 7). if the bit ttxno is set to 1 then the meterpulse is reversal. if the bit ttxno is set to 0, teletax metering is used. metering with polarity reversal: at a mode change from active state to active state with meterpulses the muslic performs a phase shift in the dc-feeding, influenced by the bit sorev (scr1, bit 4). sorev = 0: an immediate reversal ( ? hard reversal ? ) is performed sorev = 1: a soft (silent) reversal is performed (transition time programmable by cram-coefficients, default value 80 ms)
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 130 2000.07.06 preliminary teletax metering injection (not available with muslic-s): for countries with teletax metering the muslic-e provides either a 12 or 16 khz signal which is selectable by the bit ttx12 (scr1, bit 6) 1) . the amplitude of this teletax signal is programmable up to 10 vrms at the ring/tip wire of the ahv-slic. the muslic filters the teletax pulses in transmit direction, too. the slope of the pulses are internally shaped so that the noise during switching and transmission is less than 1 mv. with the bit nosl (scr1-5) the slope can be switched off. in that case the switching noise is not defined (for signalling only). 1) note, that the right teletax coefficient set (via cop-command) must be provided, too.
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 131 2000.07.06 preliminary 5.5 ringing mode scr10: (m0/m1/m2=1/0/0,1/0/1) the muslic generally supports balanced and unbalanced ringing. if the muslic is set to ringing mode, the ac-loop is turned off and the dc-loop is automatically opened. balanced ringing (not available with muslic-s) the sine wave of the ringing is generated in the mupp c. the frequency and the amplitude are free programmable between 16 and 70 hz and up to 85 vrms at the ring/ tip wire, respectively. the dc offset voltage is programmable. if the ring burst on command is sent to the mupp ? via scr10 the begin ( ? ring burst on ? ) and the end ( ? ring pause ? ) of the ring burst is automatically synchronized at the voltage zero crossing. if the dc-current at the it-pin exceeds the programmed value, off-hook is detected within 2 periods of the ringing frequency and the ring burst is switched off. if off-hook is detected the muslic remains in the ringing pause mode (no evaluation of the dup- counter is performed). unbalanced ringing the ringing voltage is generated by an external ring generator. to connect this generator to the ring/tip wires usually relays have to be used. for controlling the relays the muslic offers the following functions: if the rexten bit (xr2 bit 7) is set to 1 the io1 pin of the mupp ? will be an input for the zero crossing signal. qap pins i/o1-a...d are controlled by the scr10, bit 4 (m2 bit) and offers a zero crossed ring burst on/off control signal. ? improved support of external ringing delay ring delay coefficients are used to compensate the delay of the ring relay. this is important to guarantee that the ring generator is disconnencted from the line at zero crossing of the ringing signal. when ring burst on (rbo) is detected, the output pin io1 of the qap is low active to drive directly the ring relay.
peb 3465, peb 31666/4, peb 4166/4 muslic operating modes preliminary data sheet 132 2000.07.06 preliminary 5.6 ground start scr10: (m0/m1/m2=0/0/1) changing into the ground start mode by programming the scr10 (m2 = 1, m1 and m0 = 0) the active mode is chosen and the ternary slic-interface is set to high impedance of the tip output (hit: c1 = vom, c2 = voh). 5.7 changing modes the dup counter responsible for filtering the hook status is loaded with the double of the programmed value if any change between the modes pdn, active or ringing or if one of the following crossovers occurs: reverse <----> normal polarity ground start on <----> off pdnr on <----> off fixc, hload, reset on <----> off
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 133 2000.07.06 preliminary 6 transmission characteristics the figures in this data sheet are based on the subscriber-line board requirements. the proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) needs a complete knowledge of muslic analog environment. unless otherwise stated, the transmission characteristics parameters are guaranteed within the test conditions and a temperature range of t a =0 to 70 c. the functionality of muslic is guaranteed for t a = ? 40 to 85 c. test conditions t a =25 c; v ddi = v dda = v ddb = v ddc = v ddd = 5 v 5%; v ss = ? 5v 10%; v dd = 3.3 v + 5% gndi = gnda = gndb = gndc = gndd = 0 v h im , h th , h frx , h frr , ar, ax will be defined to meet the 0 dbm0 specification. f = 1004 hz; 0 dbm0; a-law; a 0 dbm0 ac signal in transmit direction is equivalent to 2 0.775 vrms and in receive direction equivalent to 0.775 vrms (referred to 600 ? ). figure 32 transmission characteristics 0 dbm0| muslic = 0 dbm0| 600 ? = 0.775 vrms for receive direction. 0 dbm0| muslic = 0 dbm0| 600 ? = 0.775 vrms for transmit direction. note: to meet the typical values of all programmable parameters (marked with 1) ) listed in the following tables it is necessary to calculate the coefficients by using muslicos. ezm07116.emf 0.775v rms tip ring 2 0.775v rms 600 transmit (x) 0dbm0 receive (r) 0dbm0 c ahv-slic peb 4166 peb 4164 qap peb 3465 muppc peb 31664 peb 31666 600 50 50 50 50 18n 18n
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 134 2000.07.06 preliminary 6.1 transmission values parameter symbol limit values unit test condition min. typ. max. 2-wire port (2 = 100 ? r p incl.) transmission performance overload level v tr 2.3 ?? vrms 300 hz to 4 khz return loss (2-wire) r l 17 ?? db 300 hz to 500 hz r l 22 ?? db 500 hz to 2 khz r l 22 ?? db 2 khz to 3.4 khz insertion loss transmit gain g t ? 0.3 ? 0.3 db 0 dbm0, 1 khz receive gain g r ? 0.3 ? 0.3 db 0 dbm0, 1 khz insertion loss versus frequency relative to 1 khz transmit gain g t 1) see chapter 6.2 0 dbm0, 0.3 to 3.4 khz receive gain g r 1) see chapter 6.2 0 dbm0, 0.3 to 3.4 khz gain/loss programmability transmit absolute ? 3 ...+ 3 dbr step size t x 1) ?? 1/16 db voice band receive absolute 0 ?? 12 dbr step size r x 1) ?? 1/16 db voice band
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 135 2000.07.06 preliminary gain linearity relative to 1 khz, ? 10 dbm0 transmit gain g t 1) see chapter 6.3 ? 55 dbm0 to +3dbm0 receive gain g r 1) see chapter 6.3 ? 55 dbm0 to +3dbm0 absolute group delay distortion see chapter 6.4 overload compression a/a oc see chapter 6.5 longitudinal balance muslic, -e, -s l-t 52 53 ? db 300 hz to 3.4 khz muslic-e2, -s2 l-t 58 63 ? db at 1020 hz transversal to longitudinal t-l 46 ?? db 300hz to 4khz longitudinal signal generation 4-l 46 ?? db 300hz to 4khz parameter symbol limit values unit test condition min. typ. max.
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 136 2000.07.06 preliminary out-of-band noise single frequency inband ? 25 dbm0 transversal v tr ??? 50 dbm 12 khz to 200 khz longitudinal v tr ??? 50 dbm 12 khz to 200 khz metering injection 1) impulse noise during switching v tr ?? 1 mv psophometrically weighted metering signal v ttx rl 1) 4.5 4.85 5.2 vrms 12/16 khz, r l =200 ? (see figure 33 ) at 2-, 4-wire interface v tx ?? 1 mv psophometrically weighted harmonic distortion ?? 5% ringing injection transfer gain error g rng ? 0.5 0.3 0.5 db z l =1200 ? ringing injection v tr 1) 60 63 66 vrms 16 hz to 50 hz (without load) superimposed dc voltage v rdc 1) 20 22 24 v r l = 10 k ? harmonic distortion thd ?? 5% z l = 1 k ? || 6 f ring trip function 1) detection time and delay after 12 ms ? 2 periods the ringing to off- hook status ?? 2 periods 1) not available in muslic-s parameter symbol limit values unit test condition min. typ. max.
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 137 2000.07.06 preliminary 2-wire port and pcm side total harmonic distortion 2- to 4-wire t hd4 ?? ? 46 db ? 7 dbm0, 0.3 to 3.4 khz 4- to 2-wire t hd2 ?? ? 46 db ? 7 dbm0, 0.3 to 3.4 khz idle channel noise 2-wire port (receive) a-law v tr ?? ? 70 dbmp psophometric (idle code + 0) ?law v tr ?? 20 dbrnc c-message (idle code + 0) pcm side (transmit) a-law n tp ?? ? 67 dbmp psophometric ( v in =0) ?law n tc ?? 20 dbrnc c - message ( v in =0) signal to total distortion ratio input connection: l i =0dbr s/d see chapter 6.6 ? 45 dbm0 to 0 dbm0 output connection: l o = ? 7dbr s/d see chapter 6.6 ? 45 dbm0 to 0 dbm0 parameter symbol limit values unit test condition min. typ. max.
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 138 2000.07.06 preliminary battery feeding v bat = ? 68 v, v h =+52 v power down mode (pdnr) tip to v bgnd, ring to v bat resistance r s 4.2 5 5.8 k ? active mode without calibration i loop accuracy i l 1) 23 2) 25 27 2) ma i lim2 = 25 ma i loop accuracy i l 1) 27 2) 30 33 2) ma i lim3 = 30 ma i loop accuracy i l 1) 41 2) 45 49 2) ma i lim4 = 45 ma current limitation ahv-slic i max 90 ? 120 ma wire to ground transition time t off 0.5 ? 1.5 ms on- to off-hook boost battery mode loop current same as active state output voltage v tr 1) 78 ? 86 v i line = 20 ma indication thresholds off-hook indication off-hook current i det 1) 7911ma hysteresis ? 2 ? ma ground key indication ground key current i det 1) 10 17 24 ma ring trip indication current threshold 1 i det 1) 6 7 8 ma short line + bat. charging parameter symbol limit values unit test condition min. typ. max.
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 139 2000.07.06 preliminary figure 33 voltage amplitude of teletax metering power supply rejection ratio v ripple = 100 mvpp vdd referred to agnd psrr 40 ?? db 50 hz to 4 khz vss referred to agnd psrr 40 ?? db 50 hz to 4 khz vbat referred to agnd psrr 40 ?? db 50 hz to 4 khz vbat2 referred to agnd 40 ?? db 50 hz to 4 khz vh referred to agnd psrr 40 ?? db 50 hz to 4 khz bgnd referred to agnd psrr 40 ?? db 50 hz to 4 khz 1) programmable parameter. 2) an offset calibration has to be performed in order to guarantee these min/max values. parameter symbol limit values unit test condition min. typ. max. tip ring transm it (x) 0dbm0 receive (r) 0dbm0 c ahv- slic peb 4166 qap peb 3465 mupp c peb 31666 100 100 200 v ttxab v ttxrl ezm07125.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 140 2000.07.06 preliminary 6.2 frequency response transmit: reference frequency 1 khz, signal level ? 10 dbm0 , h frx =1 figure 34 frequency response transmit receive: reference frequency 1 khz, signal level ? 10 dbm0, h frr =1 figure 35 frequency response receive 1.0 -1.0 0 0.9 2.0 frequency khz attenuation db 3.0 2.0 3.4 0.3 3.6 .2 .4 .6 2.4 -0.3 0.3 0.4 0.7 1.4 x ezm03010.wmf 1.0 -1.0 0 0.9 2.0 frequency khz attenuation db 3.0 2.0 3.4 0.3 3.6 .2 .4 .6 2.4 -0.3 0.3 0.4 0.7 1.4 x 0.65 ezm03011.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 141 2000.07.06 preliminary 6.3 gain tracking (receive and transmit) the gain deviations stay within the limits in the figures below. measured with sine wave f = 1004 hz reference level is ? 10 dbm0. figure 36 gain tracking (receive and transmit) 0 -55 -50 -30 -20 -10 0 +1.0 +2.0 +3 input level dbm0 g db +0.6 -40 +0.3 +1.6 x -2.0 -1.6 -0.6 -1.0 -0.3 ezm03012.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 142 2000.07.06 preliminary 6.4 group delay maximum delays when the qap and the mupp ? are operating with h th =h im = 0 and h frr =h frx = 1 including delay through a/d- and d/a converters. specific filter programming may cause additional group delays. group delay deviations stay within the limits in the figures below. group delay absolute values: signal level ? 10 dbm0, f test @ t gmin figure 37 group delay distortion (receive and transmit) table 14 group delay parameter symbol limit values unit test condition min. typ. max. transmit delay d xa ? 527.5 ? ? f = 1.5 khz receive delay d ra ? 437.5 ? ? f = 1.5 khz 1.0 150 300 frequency khz group delay distortion us 2.8 0.5 0.6 2.6 100 ezm03013.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 143 2000.07.06 preliminary 6.5 overload compression measured with sine wave f =1004hz figure 38 overload compression transmit 0 1.0 2.0 4.0 5.0 6.0 7.0 8.0 9.0 -1.0 0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 1.0 3.0 3.4 acceptable region 0.25 -0.25 fundamental input power (dbm0) fundamental output power (dbm0) ezm03014.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 144 2000.07.06 preliminary 6.6 total distortion the signal to distortion ratio exceeds the limits in the following figure: receive: measured with sine wave f = 1004 hz. (c-message weighted for ?law, pso- phometrically weighted for a ? law). the mean relative level is ? 7dbr. figure 39 total distortion receive ar = 7 dbr 20.0 -50 -30 -20 -10 0 0 10.0 30.0 input level dbm0 s/d db -40 22.0 17.0 35.0 -45 34.4 30.9 40 ezm03015.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 145 2000.07.06 preliminary transmit : measured with sine wave f = 1004 hz. (c-message weighted for ? ?law, psophometrically weighted for a-law). the mean relative level is 0 dbr. figure 40 total distortion transmit ax = 0 dbr 20.0 -50 -30 -20 -10 0 0 10.0 30.0 input level dbm0 s/d db -40 21,5 35.0 -45 34.8 33.8 40 26,5 ezm03016.wmf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 146 2000.07.06 preliminary 6.7 out-of-band signals at analog output (receive) with a 0 dbm0 sine wave with frequency f (300 hz to 3.4 khz) applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least x db below a 0 dbm0, 1 khz sine wave reference signal at the analog output. figure 41 out-of-band signals at analog output (receive) 0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 200 db 35 30 25 20 15 10 0 receive out of band discrimination x 45 28 5 khz f 40 3.4 ? 4.6 khz: x 14 ? 4000 f ? 1200 -------------------- - sin 1 ? = itd09762.emf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 147 2000.07.06 preliminary 6.8 out-of-band signals at analog input (transmit) with a 0 dbm0 out-of-band sine wave signal with frequency f (< 100 hz or 3.4 khz to 100 khz) applied to the analog input, the level of any resulting frequency component at the digital output will stay at least x db below a 0 dbm0, 1 khz sine wave reference signal at the analog input. 1) figure 42 out-of-band signals at analog input (transmit) 1) poles at 12 khz 150 hz respectively 16 khz 150 hz and harmonics will be provided 0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 100 40 35 32 30 25 20 15 10 0 transmit out of band discrimination x khz f db 3.4 ? 4.0 khz: x 14 ? 4000 f ? 1200 -------------------- - sin 1 ? = 4.0 ? 4.6 khz: x18 ? 4000 f ? 1200 -------------------- - sin 7 9 -- - ? = itd09763.emf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 148 2000.07.06 preliminary 6.9 out-of-band ringing distortion figure 43 out-of-band ringing distortion 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0.1 0 1 10 100 khz f ringing distortion out of band discrimination x 1000 0,025 50db 40db 26db ezm07124.emf
peb 3465, peb 31666/4, peb 4166/4 muslic transmission characteristics preliminary data sheet 149 2000.07.06 preliminary 6.10 terminal balance return loss the quality of transhybrid-balancing is very sensitive to deviations in gain and group delay ? deviations inherent to the muslic a/d- and d/a-converters as well as to all external components used on a line card. measurement of muslic transhybrid-loss: a 0dbm0 sine wave signal with a frequency in the range between 300 ? ? 3400 hz is applied to the digital input. the resulting echo measured at the digital output is at least x db below the level of the digital input signal as shown in the table below. parameter symbol limit values unit test condition min. typ. transhybrid loss at 500 hz thl 500 33 50 db transhybrid loss at 2500 hz thl 2500 29 44 db transhybrid loss at 3000 hz thl 3000 27 42 db
peb 3465, peb 31666/4, peb 4166/4 muslic test features preliminary data sheet 150 2000.07.06 preliminary 7 test features 1) note: test functions are not available with muslic-s 1) for detaild information about line and board testing please refer to the application note "line testing with muslic" table 15 levelmeter-function no. test result loops settings switches description 1. level metering ac pcm mva, rlm0/1 ac loop itime lmbp lmnotch lm2pcm lmsel0/1 elm ente on elm on after programming the settings and release with the ente the levelmetering will be started by elm = 1. the end of measurement is shown by mva, rlm0/1 and the result can be sent to the corresponding-voice channel. itime determines the integration time either 16 ms or 256 ms. 2. level metering dc pcm mva, rlm0/1 dc loop lp03, lp5, dispofi, pcm2dc dcad16 eramp erect lm2pcm lmsel0/1 elm f ring ente on elm on after programming the settings and release with the ente the levelmetering will be started by elm = 1. the measurement time is programmable using the ring generator. the end of measurement is shown by mva, rlm0/ 1 and the result can be sent to the corresponding-voice channel. includes measurement of offset, and ringer capacitance. 3. level metering ttx pcm mva, rlm0/1 dc loop elm ttxl lmsel0/1 lm2pcm pcm2dc ente on elm on after programming the settings and release with the ente the levelmetering will be started by elm = 1. the measurement time is programmable by itime either 16 ms or 256 ms. the end of measurement is shown by mva, rlm0/1 and the result can be sent to the corresponding-voice channel. by setting ttxl and correct programming of the im-filters the ttx current is measured directly.
peb 3465, peb 31666/4, peb 4166/4 muslic package outlines preliminary data sheet 151 2000.07.06 preliminary 8 package outlines 8.1 peb 3465 (qap) figure 44 package outline: peb 3465 (qap) 0.65 0.3 12.35 0.1 2 2.45 max 1 80 index marking 17.2 14 0.25 min +0.1 0.88 1) 0.6x45? 1) does not include plastic or metal protrusions of 0.25 max per side a-b 0.2 h d 4x a-b 0.2 d 80x a b d c 0.12 80x d a-b m c 1) 14 17.2 -0.05 h 7?max -0.02 +0.08 0.15 ?.08 p-mqfp-80-1 (plastic metric quad flat package) gpm05249.ps sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information. dimensions in mm smd = surface mounted device
peb 3465, peb 31666/4, peb 4166/4 muslic package outlines preliminary data sheet 152 2000.07.06 preliminary 8.2 peb 31666 / peb 31664 (mupp c) figure 45 package outline: peb 31666 / peb 31664 (mupp c) p-mqfp-64-1 (plastic metric quad flat package) gpm05250.ps sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information. dimensions in mm smd = surface mounted device
peb 3465, peb 31666/4, peb 4166/4 muslic package outlines preliminary data sheet 153 2000.07.06 preliminary 8.3 peb 4166 / peb 4164 (ahv-slic) figure 46 package outline: peb 4166 / peb 4164 (ahv-slic) p-dso-20-5 (plastic dual small outline) gpm05755.ps sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information. dimensions in mm smd = surface mounted device
peb 3465, peb 31666/4, peb 4166/4 muslic glossary preliminary data sheet 154 2000.07.06 preliminary 9 glossary act active mode adc analog digital converter agr attenuation receive agx attenuation transmit ahv-slic advanced high voltage subscriber line interface circuit ar attenuation receive asic application specific integrated circuit ax attenuation transmit bb boosted battery c1, c2, c3 digital interface between qap and ahv-slic cmp compander codec coder decoder comp comparator (testloops, levelmetering) cop coefficient operation cram coefficient ram dac digital analog converter dtag deutsche telecom ag dcchar dc characteristic block dd data downstream dsp digital signal processor du data upstream dup data upstream persistency counter dupgnk data upstream persistency counter for gnk exp expander frr frequency response receive filter frx frequency response transmit filter fsc frame sync. gnk ground key i1 fixed input pin il longitudinal current input io user programmable i/o pin it transversal current input (for ac and dc)
peb 3465, peb 31666/4, peb 4166/4 muslic glossary preliminary data sheet 155 2000.07.06 preliminary itac transversal current input (for ac) lp03 low pass 0.3 hz lp5 low pass 5 hz lssgr local area transport access switching system generic requirements mclk master clock muppc multi channel processor for pots muslic multi channel subscriber line interface circuit muslicos muslic oriented software o1 fixed output pin pcm pulse code modulation pdn power down pdn pdn pin (sets the ahv-slic to power down) pots plain old telephone service prefi antialiasing pre filter qap quad analog pots rb ring burst res reset rng ring generator rref external resistor to gnda scr status configuration register slic subscriber line interface circuit slxc summary line card outputs sop status operation stcr status test configuration register tcr transfer configuration register tst1 test pin tg tone generator th transhybrid balancing thfix transhybrid balancing filter (fixed) top transfer operation ts time slot
peb 3465, peb 31666/4, peb 4166/4 muslic glossary preliminary data sheet 156 2000.07.06 preliminary ttx teletax vbim battery image input vb/2 half battery voltage input (programmable voltage threshold, see also scr2, bit 7) x transmit filter (programmable)
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